📄 eprcrt0.s
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MOVE.L #$80000000,D0 ;// enable the cache
MOVEC D0,CACR
MOVE.L #$0,D0 ;// Disable ACR0, ACR1
MOVEC D0,ACR0
MOVEC D0,ACR1
MOVE.L #($70000000) ,D0 ;// 8K SRAM
MOVEC D0,RAMBAR
MOVE.L #(SIM_BASE_ADDR+1),D0 ;// MBAR
MOVEC D0,MBAR
MOVE.B #$e1,D0 ;//PAR
MOVE.B D0, SIM_BASE_ADDR+$CB
MOVE.B #$85,D0 ;//ICR1
MOVE.B D0, SIM_BASE_ADDR+$14
MOVE.B #$8B,D0 ;//ICR2
MOVE.B D0, SIM_BASE_ADDR+$15
MOVE.B #$8E,D0 ;//ICR3
MOVE.B D0, SIM_BASE_ADDR+$16
MOVE.B #$90,D0 ;//ICR4
MOVE.B D0, SIM_BASE_ADDR+$17
MOVE.B #$95,D0 ;// ICR5
MOVE.B D0, SIM_BASE_ADDR+$18
MOVE.B #$98,D0 ;// ICR6
MOVE.B D0, SIM_BASE_ADDR+$19
MOVE.B #$9F,D0 ;// ICR7
MOVE.B D0, SIM_BASE_ADDR+$1A
MOVE.B #$1E,D0 ;// ICR8
MOVE.B D0, SIM_BASE_ADDR+$1B
MOVE.B #$80,D0 ;// ICR9
MOVE.B D0, SIM_BASE_ADDR+$1C
MOVE.B #$80,D0 ;// ICR10
MOVE.B D0, SIM_BASE_ADDR+$1D
MOVE.B #$8C,D0 ;// ICR11
MOVE.B D0, SIM_BASE_ADDR+$1E
MOVE.B #$8E,D0 ;// ICR12
MOVE.B D0, SIM_BASE_ADDR+$1F
MOVE.B #$8D,D0 ;// ICR13
MOVE.B D0, SIM_BASE_ADDR+$20
MOVE.W #$0300,D0 ;// DCRR
MOVE.W D0, SIM_BASE_ADDR+$46
MOVE.W #$0200,D0 ;// DCTR
MOVE.W D0, SIM_BASE_ADDR+$4A
MOVE.W #$0000,D0 ;// DCAR0
MOVE.W D0, SIM_BASE_ADDR+$4C
MOVE.L #$003E0000,D0 ;// DCMR0
MOVE.L D0, SIM_BASE_ADDR+$50
MOVE.B #$17,D0 ;// DCCR0
MOVE.B D0, SIM_BASE_ADDR+$57
MOVE.W #$0080,D0 ;// CSAR0
MOVE.W D0, SIM_BASE_ADDR+$64
MOVE.L #$3F0000,D0 ;// CSMR0
MOVE.L D0, SIM_BASE_ADDR+$68
MOVE.W #$1103,D0 ;// CSCR0
MOVE.W D0, SIM_BASE_ADDR+$6E
; MOVE.W #$0a00,D0 ;// CSAR1
; MOVE.W D0, SIM_BASE_ADDR+$70
;
; MOVE.L #$001f0020,D0 ;// CSMR1
; MOVE.L D0, SIM_BASE_ADDR+$74
; MOVE.W #$1d43,D0 ;// CSCR1
; MOVE.W D0, SIM_BASE_ADDR+$7A
MOVE.W #$1000,D0 ;// CSAR2
MOVE.W D0, SIM_BASE_ADDR+$7C
MOVE.L #$f0000,D0 ;// CSMR2
MOVE.L D0, SIM_BASE_ADDR+$80
MOVE.W #$1143,D0 ;// CSCR2
MOVE.W D0, SIM_BASE_ADDR+$86
MOVE.W #$0060,D0
MOVE.W D0, SIM_BASE_ADDR+$88
MOVE.L #$00000000,D0
MOVE.L D0, SIM_BASE_ADDR+$8C
MOVE.W #$9d3,D0
MOVE.W D0, SIM_BASE_ADDR+$92
MOVE.W #$40,D0
MOVE.W D0, SIM_BASE_ADDR+$94
MOVE.L #$f0000,D0
MOVE.L D0, SIM_BASE_ADDR+$98
MOVE.W #$0d9f,D0
MOVE.W D0, SIM_BASE_ADDR+$9e
MOVE.W #$50,D0
MOVE.W D0, SIM_BASE_ADDR+$A0
MOVE.L #$70014,D0
MOVE.L D0, SIM_BASE_ADDR+$a4
MOVE.W #$1c3,D0
MOVE.W D0, SIM_BASE_ADDR+$aa
MOVE.W #$0d00,D0
MOVE.W D0, SIM_BASE_ADDR+$c6
BRA CODE_MOVER ;goto executing your program
;//////////////////////////////////////////////////////////////////////////
;//
;// 4. watchdog test
;//
;//////////////////////////////////////////////////////////////////////////
WATCHDOG_TESTER:
;//load the reset flag to D0 and D1
MOVE.L #RESET_FLAG, A0
MOVE.L (A0)+, D0
MOVE.L (A0), D1
;// check whether reset flag is the predefined number, if not, jump to
;// WATCHDOG_TEST, else jump to DRAM_TEST
; CMP.L #RESET_FLAG_NUMBER0, D0
; BNE WATCHDOG_TEST
; BRA DRAM_TEST
; CMP.L #RESET_FLAG_NUMBER1, D1
; BNE WATCHDOG_TEST
; BRA DRAM_TEST
WATCHDOG_TEST:
;// save predefined number in reset flag to indicate that system
;// has been powered on
; // for debug.
MOVE.B #$0fd, D0 ;// added by LLH(2000.9.30).
MOVE.B D0, SIM_BASE_ADDR+$1C9 ;// parallel port data
MOVE.L #RESET_FLAG_NUMBER0, D0
MOVE.L #RESET_FLAG_NUMBER1, D1
MOVE.L #RESET_FLAG, A0
MOVE.L D0, (A0)+
MOVE.L D1, (A0)
;// sound on 150 ms
MOVE.B #ENABLE_BUZZER, D2
MOVE.B D2, (PARALLEL_PORT).L
MOVE.L #15, D0
BSR DELAY
;// sound off
MOVE.B #DISABLE_BUZZER, D2
MOVE.B D2, (PARALLEL_PORT).L
;// Clear the FPGA init state byte.
move.b #0,d0
move.l #$3ffff0,a0
move.b d0,(a0)
;// Fire the watchdog. Ason. (2000.12.26.)
MOVE.B D0,(ENABLEWD_PORT).L
;// delay for four seconds to wait keyboard controller reset host CPU
MOVE.L #400, D0
BSR DELAY
;// if code following has been executed, the watchdog has error
BRA BEEP
;//=======================================================================
;//////////////////////////////////////////////////////////////////////////
;//
;// 5. DRAM test
;//
;//////////////////////////////////////////////////////////////////////////
;// wirte/read test of 55H and 0AAH.
;// if a wirte/read failured, set error code and stopping test immediately.
DRAM_TEST:
MOVE.L #START_ADDRESS_OF_DRAM, A0
MOVE.L #END_ADDRESS_OF_DRAM, D0
.L1:
;// write/read 55
MOVE.L #$055555555, D1
MOVE.L D1, (A0)
CMP.L (A0), D1
BNE BEEP
;// write/read AA
MOVE.L #$0AAAAAAAA, D1
MOVE.L D1, (A0)
CMP.L (A0)+, D1
BNE BEEP
CMP.L A0, D0
BHI .L1
;// wirte/read test of incremental data ( 0 through FFFFFH )
;// wirte incremental data ( 0 through FFFFFH )
MOVE.L #START_ADDRESS_OF_DRAM, A0
MOVE.L #END_ADDRESS_OF_DRAM, D0
MOVE.L #0, D1
.L2:
MOVE.L D1, (A0)+
ADDI.L #1, D1
CMP.L A0, D0
BHI .L2
;// compare incremental data ( 0 through FFFFFH )
MOVE.L #START_ADDRESS_OF_DRAM, A0
MOVE.L #END_ADDRESS_OF_DRAM, D0
MOVE.L #0, D1
.L3:
CMP.L (A0)+, D1
BNE BEEP ;//not equal, error detected, go to beep
ADDI.L #1, D1
CMP.L A0, D0
BHI .L3
;//////////////////////////////////////////////////////////////////////////
;//
;// 6. copy program in flash ROM to DRAM
;//
;//////////////////////////////////////////////////////////////////////////
CODE_MOVER:
;// source address, add by 16 to exclude SP and PC's init value
;//MOVE.L #__FLASH_BASE_ADDR + 8, A0
;//MOVE.L #$600001B8, A0
;//MOVE.B #$01 , (A0)
MOVE.L #__PROGRAM_ADDR, A0
;// destination address space, from __START_ADDRESS
;// to __END_ADDR_OF_FLASH_TO_DRAM, this space have exclude loader program
;// and section "start" code
MOVE.L #__START_ADDRESS, A1
MOVE.L #__END_ADDR_OF_FLASH_TO_DRAM, D0
.L4:
CLR.L (A1)
MOVE.L (A0)+, (A1)+
CMP.L A1, D0
BHI .L4
;// 8. jump to execute program in DRAM
JMP __crt0 ;goto executing your program
;////////////////////////////////////////////////////////////////////////////
;/* */
;/* FUNCTION */
;/* */
;/* BEEP */
;/* */
;/* DESCRIPTION */
;/* */
;/* make buzzer to sound, this routine will not return forever. */
;/* the rhythm of sound ( one cycle, unit: millisecond): */
;/* */
;/* 150 150 150 150 150 */
;/* */
;/* on: --- --- --- --- --- */
;/* off: ---- ---- -------- ---- ------....-- */
;/* */
;/* 200 200 400 200 2000 */
;/* */
;/* CALLED BY */
;/* */
;/* SELF_TEST */
;/* */
;/* CALLS */
;/* */
;/* DELAY */
;/* */
;/* INPUTS, OUTPUTS */
;/* */
;/* None */
;/* */
;/* HISTORY */
;/* */
;/* NAME DATE REMARKS */
;/* lilinghua 10-9-1999 created */
;/* */
;////////////////////////////////////////////////////////////////////////////
BEEP:
;// sound on 150 ms
MOVE.B #ENABLE_BUZZER, D2
MOVE.B D2, (PARALLEL_PORT).L
MOVE.L #15, D0
BSR DELAY
;// sound off 200 ms
MOVE.B #DISABLE_BUZZER, D2
MOVE.B D2, (PARALLEL_PORT).L
MOVE.L #20, D0
BSR DELAY
;// sound on 150 ms
MOVE.B #ENABLE_BUZZER, D2
MOVE.B D2, (PARALLEL_PORT).L
MOVE.L #15, D0
BSR DELAY
;// sound off 200 ms
MOVE.B #DISABLE_BUZZER, D2
MOVE.B D2, (PARALLEL_PORT).L
MOVE.L #20, D0
BSR DELAY
;// sound on 150 ms
MOVE.B #ENABLE_BUZZER, D2
MOVE.B D2, (PARALLEL_PORT).L
MOVE.L #15, D0
BSR DELAY
;// sound off 400 ms
MOVE.B #DISABLE_BUZZER, D2
MOVE.B D2, (PARALLEL_PORT).L
MOVE.L #40, D0
BSR DELAY
;// sound on 150 ms
MOVE.B #ENABLE_BUZZER, D2
MOVE.B D2, (PARALLEL_PORT).L
MOVE.L #15, D0
BSR DELAY
;// sound off 200 ms
MOVE.B #DISABLE_BUZZER, D2
MOVE.B D2, (PARALLEL_PORT).L
MOVE.L #20, D0
BSR DELAY
;// sound on 150 ms
MOVE.B #ENABLE_BUZZER, D2
MOVE.B D2, (PARALLEL_PORT).L
MOVE.L #15, D0
BSR DELAY
;// sound off 2000 ms
MOVE.B #DISABLE_BUZZER, D2
MOVE.B D2, (PARALLEL_PORT).L
MOVE.L #200, D0
BSR DELAY
BRA BEEP
;//=======================================================================
;////////////////////////////////////////////////////////////////////////////
;/* */
;/* FUNCTION */
;/* */
;/* DELAY */
;/* */
;/* DESCRIPTION */
;/* */
;/* delay routine */
;/* */
;/* CALLED BY */
;/* */
;/* SELF_TEST, BEEP */
;/* */
;/* CALLS */
;/* */
;/* None */
;/* */
;/* INPUTS */
;/* */
;/* D0: delayed time( in 10 milliseconds) */
;/* */
;/* OUTPUTS */
;/* */
;/* None */
;/* */
;////////////////////////////////////////////////////////////////////////////
DELAY:
MOVE.L #$01a000, D1
INNER_LOOP:
SUBQ.L #1, D1
BHI INNER_LOOP
SUBQ.L #1, D0
BHI DELAY
RTS
;//=========================================================================
;////////////////////////////////////////////////////////////////////////////
;// section ".text" is C program assembly startup code for
;// an embedded environment.
;// -------------------------------------------------------
.text
__crt0:
;// initialize sp to value from link editor command file
move.l #___SP_INIT,a7
;// initialize a5 to sdata (provided by linker)
move.l #__SDA_BASE_,a5
jsr ___init_main ;// dummy to pull in main() as soon as possible
section .init,2,C
XDEF ___init
ALIGN 4
___init:
section .fini,2,C
;// Return from __init
rts
XDEF ___fini
___fini:
section .eini,2,C
;// Return from ___fini
rts
;//=========================================================================
;//end of startup self-test
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