📄 eprcrt0.s
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;////////////////////////////////////////////////////////////////////////////
;/* */
;/* FILE NAME VERSION */
;/* */
;/* crt0.s Version CE */
;/* */
;/* DESCRIPTION */
;/* */
;/* This file contains the host board startup self-test, target */
;/* processor dependent initialization routines and data. */
;/* */
;/* FUNCTIONS */
;/* */
;/* SELF_TEST startup self-test */
;/* BEEP buzzer beep in a predefineded manner */
;/* DELAY a software 10ms delay routine */
;/* */
;////////////////////////////////////////////////////////////////////////////
;// constant define
;// start and end address of DRAM
START_ADDRESS_OF_DRAM = 0
END_ADDRESS_OF_DRAM = $400000
;// SIM registers base address
SIM_BASE_ADDR = $60000000
;// space for saving checksum(last four bytes of flash ROM)
CHECK_SUM = $A00000 - $10000 - 4
;// reset flag's address, the reset flag is a 64-bit number
RESET_FLAG = $400000 - 8
;//the predefined number for reset flag
RESET_FLAG_NUMBER0 = $01234567
RESET_FLAG_NUMBER1 = $89ABCDEF
;// constant define for alarm. LLH.2000.9.30
PARALLEL_PORT = (SIM_BASE_ADDR + $1C9)
ENABLE_BUZZER = $0FD
DISABLE_BUZZER = $0FF
;// constant defined for watchdog. Ason. 2000.12.26.
ENABLEWD_PORT = $9c0004
DISABLEWD_PORT = $9c0000
;//////////////////////////////////////////////////////////////////////////
;//
;// define the register test macro:
;// each general-purpose register will be tested by six hex number(ffff0000,
;// ff00ff00, f0f0f0f0, cccccccc, aaaaaaaa, 55555555) to detect cross link
;// between bits in register
;//
;//////////////////////////////////////////////////////////////////////////
TEST_REGISTER: macro REGISTER
MOVE.L #$FFFF0000, REGISTER
CMP.L #$FFFF0000, REGISTER
BNE REGISTER_ERROR
MOVE.L #$FF00FF00, REGISTER
CMP.L #$FF00FF00, REGISTER
BNE REGISTER_ERROR
MOVE.L #$F0F0F0F0, REGISTER
CMP.L #$F0F0F0F0, REGISTER
BNE REGISTER_ERROR
MOVE.L #$CCCCCCCC, REGISTER
CMP.L #$CCCCCCCC, REGISTER
BNE REGISTER_ERROR
MOVE.L #$AAAAAAAA, REGISTER
CMP.L #$AAAAAAAA, REGISTER
BNE REGISTER_ERROR
MOVE.L #$55555555, REGISTER
CMP.L #$55555555, REGISTER
BNE REGISTER_ERROR
endm
;//=======================================================================
;// The section "start"(exclude first two instructions) will be run in the
;// flash ROM to initiate hardware,you can change it as you wanted
PSECT
XDEF _START
XDEF start
ALIGN 4
.section start
start:
_START:
; move.l #__SP_LOADER, a7 ;// this two instructions will be runned in the
; JSR _loader ;// SDS Debugger environment to load your
;// program to flash ROM
;////////////////////////////////////////////////////////////////////////////
;/* */
;/* FUNCTION */
;/* */
;/* SELF_TEST the startup self-test function */
;/* */
;/* DESCRIPTION */
;/* */
;/* The function is executed as following: */
;/* */
;/* 1. condition code(flags) and condition instructions test */
;/* 2. CPU registers test */
;/* 3. configuration registers initializing */
;/* 4. watchdog test */
;/* 5. DRAM test( read/write test of (AA, 55) and incremental data ) */
;/* 6. copy program in flash ROM to DRAM */
;/* 7. checksum test of program in DRAM */
;/* 8. jump to execute program in DRAM */
;/* */
;/* In the test steps(include step 1,2,4,5,7), if any error is */
;/* detected, system will set a buzzer to alarm and stay there */
;/* */
;/* CALLED BY */
;/* */
;/* This function will be executed immediately after system is */
;/* powered on or reset. */
;/* */
;/* CALLS */
;/* */
;/* BEEP, DELAY */
;/* */
;/* INPUTS, OUTPUTS */
;/* */
;/* None */
;/* */
;/* HISTORY */
;/* */
;/* NAME DATE REMARKS */
;/* guoyanmei 6-13-1998 created */
;/* lilinghua 10-9-1999 added more self-test routine */
;/* */
;////////////////////////////////////////////////////////////////////////////
;////////////////////////////////////////////////////////////////////////////
;/* */
;/* FUNCTION */
;/* */
;/* SELF_TEST the startup self-test function */
;/* */
;/* DESCRIPTION */
;/* */
;/* The function is executed as following: */
;/* */
;/* 1. condition code(flags) and condition instructions test */
;/* 2. CPU registers test */
;/* 3. configuration registers initializing */
;/* 4. watchdog test */
;/* 5. DRAM test( read/write test of (AA, 55) and incremental data ) */
;/* 6. copy program in flash ROM to DRAM */
;/* 7. checksum test of program in DRAM */
;/* 8. jump to execute program in DRAM */
;/* */
;/* In the test steps(include step 1,2,4,5,7), if any error is */
;/* detected, system will set a buzzer to alarm and stay there */
;/* */
;/* CALLED BY */
;/* */
;/* This function will be executed immediately after system is */
;/* powered on or reset. */
;/* */
;/* CALLS */
;/* */
;/* BEEP, DELAY */
;/* */
;/* INPUTS, OUTPUTS */
;/* */
;/* None */
;/* */
;/* HISTORY */
;/* */
;/* NAME DATE REMARKS */
;/* guoyanmei 6-13-1998 created */
;/* lilinghua 10-9-1999 added more self-test routine */
;/* */
;////////////////////////////////////////////////////////////////////////////
;// initiate CPU registers
SELF_TEST:
MOVE #$2700,SR ;// IN CASE OF
MOVE.L A7,D1 ;// Save A7. Needed for set of VBR
MOVE.L #$00000000,A7 ;// due to chip errata.
MOVEC A7,VBR ;// Set the VBR.
MOVE.L D1,A7 ;// Restore A7
;//////////////////////////////////////////////////////////////////////////
;//
;// 1. condition code(flags) and condition instructions test
;//
;//////////////////////////////////////////////////////////////////////////
;// carry flag and BCS
MOVE #1, CCR ;//jump never test
BCS GOOD_BCS
BRA CCR_ERROR
GOOD_BCS:
MOVE #0, CCR
BCS CCR_ERROR ;//jump always test
;// carry flag and BCC
MOVE #0, CCR
BCC GOOD_BCC
BRA CCR_ERROR
GOOD_BCC:
MOVE #1, CCR
BCC CCR_ERROR
;// zero flag and BEQ
MOVE #4, CCR
BEQ GOOD_BEQ
BRA CCR_ERROR
GOOD_BEQ:
MOVE #0, CCR
BEQ CCR_ERROR
;// BGE
MOVE #0, CCR
BGE GOOD_BGE
BRA CCR_ERROR
GOOD_BGE:
MOVE #8, CCR
BGE CCR_ERROR
;// BGT
MOVE #0, CCR
BGT GOOD_BGT
BRA CCR_ERROR
GOOD_BGT:
MOVE #8, CCR
BGT CCR_ERROR
;// BHI
MOVE #0, CCR
BHI GOOD_BHI
BRA CCR_ERROR
GOOD_BHI:
MOVE #1, CCR
BHI CCR_ERROR
;// BLE
MOVE #4, CCR
BLE GOOD_BLE
BRA CCR_ERROR
GOOD_BLE:
MOVE #0, CCR
BLE CCR_ERROR
;// BLS
MOVE #1, CCR
BLS GOOD_BLS
BRA CCR_ERROR
GOOD_BLS:
MOVE #0, CCR
BLS CCR_ERROR
;// BLT
MOVE #8, CCR
BLT GOOD_BLT
BRA CCR_ERROR
GOOD_BLT:
MOVE #0, CCR
BLT CCR_ERROR
;// BMI
MOVE #8, CCR
BMI GOOD_BMI
BRA CCR_ERROR
GOOD_BMI:
MOVE #0, CCR
BMI CCR_ERROR
;// BNE
MOVE #0, CCR
BNE GOOD_BNE
BRA CCR_ERROR
GOOD_BNE:
MOVE #4, CCR
BNE CCR_ERROR
;// BPL
MOVE #0, CCR
BPL GOOD_BPL
BRA CCR_ERROR
GOOD_BPL:
MOVE #8, CCR
BPL CCR_ERROR
;// BVC
MOVE #0, CCR
BVC GOOD_BVC
BRA CCR_ERROR
GOOD_BVC:
MOVE #2, CCR
BVC CCR_ERROR
;// BVS
MOVE #2, CCR
BVS GOOD_BVS
BRA CCR_ERROR
GOOD_BVS:
MOVE #0, CCR
BVS CCR_ERROR
BRA REGISTERS_TEST
CCR_ERROR:
BRA BEEP
;//=======================================================================
;//////////////////////////////////////////////////////////////////////////
;//
;// 2. CPU registers test
;//
;//////////////////////////////////////////////////////////////////////////
;// detect cross link between bits in register( general-purpose )
REGISTERS_TEST:
TEST_REGISTER A0
TEST_REGISTER A1
TEST_REGISTER A2
TEST_REGISTER A3
TEST_REGISTER A4
TEST_REGISTER A5
TEST_REGISTER A6
TEST_REGISTER A7
TEST_REGISTER D0
TEST_REGISTER D1
TEST_REGISTER D2
TEST_REGISTER D3
TEST_REGISTER D4
TEST_REGISTER D5
TEST_REGISTER D6
TEST_REGISTER D7
BRA REGISTERS_CROSS_LINK
REGISTER_ERROR:
BRA BEEP
;// detect cross link between general-purpose registers
REGISTERS_CROSS_LINK:
MOVE.L #0, D0
MOVE.L #1, D1
MOVE.L #2, D2
MOVE.L #3, D3
MOVE.L #4, D4
MOVE.L #5, D5
MOVE.L #6, D6
MOVE.L #7, D7
MOVE.L #8, A0
MOVE.L #9, A1
MOVE.L #10, A2
MOVE.L #11, A3
MOVE.L #12, A4
MOVE.L #13, A5
MOVE.L #14, A6
MOVE.L #15, A7
CMP.L #0, D0
BNE REGISTER_ERROR
CMP.L #1, D1
BNE REGISTER_ERROR
CMP.L #2, D2
BNE REGISTER_ERROR
CMP.L #3, D3
BNE REGISTER_ERROR
CMP.L #4, D4
BNE REGISTER_ERROR
CMP.L #5, D5
BNE REGISTER_ERROR
CMP.L #6, D6
BNE REGISTER_ERROR
CMP.L #7, D7
BNE REGISTER_ERROR
CMP.L #8, A0
BNE REGISTER_ERROR
CMP.L #9, A1
BNE REGISTER_ERROR
CMP.L #10, A2
BNE REGISTER_ERROR
CMP.L #11, A3
BNE REGISTER_ERROR
CMP.L #12, A4
BNE REGISTER_ERROR
CMP.L #13, A5
BNE REGISTER_ERROR
CMP.L #14, A6
BNE REGISTER_ERROR
CMP.L #15, A7
BNE REGISTER_ERROR
;// set/clear test and detect cross link between bits (M, I[0:2], X,
;// N, Z, V, C) of SR.
;// Note: bit15,12 cannot be tested, bit14,11,7,6,5 are always zero
CLR.L D0
MOVE.W #($FFFF&$371F), SR
MOVE.W SR, D0
CMP.L #($FFFF&$371F), D0
BNE REGISTER_ERROR
MOVE.W #($FF00&$371F), SR
MOVE.W SR, D0
CMP.L #($FF00&$371F), D0
BNE REGISTER_ERROR
MOVE.W #($F0F0&$371F), SR
MOVE.W SR, D0
CMP.L #($F0F0&$371F), D0
BNE REGISTER_ERROR
MOVE.W #($ECCC&$371F), SR
MOVE.W SR, D0
CMP.L #($ECCC&$371F), D0
BNE REGISTER_ERROR
MOVE.W #($AAAA&$371F), SR
MOVE.W SR, D0
CMP.L #($AAAA&$371F), D0
BNE REGISTER_ERROR
MOVE.W #($7555&$371F), SR
MOVE.W SR, D0
CMP.L #($7555&$371F), D0
BNE REGISTER_ERROR
;//=======================================================================
;//////////////////////////////////////////////////////////////////////////
;//
;// 3. configuration registers initializing
;//
;//////////////////////////////////////////////////////////////////////////
MOVE.L #$1000000,D0 ;// invalidate cache contents
MOVEC D0,CACR
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