pipemult.tan.rpt

来自「该源码实现了一个8*8位的乘法器」· RPT 代码 · 共 228 行 · 第 1/5 页

; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                                                ;
+------------------------------+-------+---------------+----------------------------------+-------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time                      ; From                                                                                                              ; To                                                                                                                ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+----------------------------------+-------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------+------------+----------+--------------+
; Worst-case tsu               ; N/A   ; None          ; 2.888 ns                         ; wraddress[3]                                                                                                      ; lpm_ram_dp0:inst1|altsyncram:altsyncram_component|altsyncram_g691:auto_generated|ram_block1a15~porta_address_reg3 ;            ; clk1     ; 0            ;
; Worst-case tco               ; N/A   ; None          ; 9.828 ns                         ; lpm_ram_dp0:inst1|altsyncram:altsyncram_component|altsyncram_g691:auto_generated|ram_block1a15~portb_address_reg4 ; q[5]                                                                                                              ; clk1       ;          ; 0            ;
; Worst-case th                ; N/A   ; None          ; -1.932 ns                        ; datab[1]                                                                                                          ; mult:inst|lpm_mult:lpm_mult_component|mult_m5q:auto_generated|mac_mult2~OBSERVABLEDATAB_REGOUT1                   ;            ; clk1     ; 0            ;
; Clock Setup: 'clk1'          ; N/A   ; None          ; 170.13 MHz ( period = 5.878 ns ) ; mult:inst|lpm_mult:lpm_mult_component|mult_m5q:auto_generated|mac_mult2~OBSERVABLEDATAB_REGOUT7                   ; lpm_ram_dp0:inst1|altsyncram:altsyncram_component|altsyncram_g691:auto_generated|ram_block1a15~porta_datain_reg12 ; clk1       ; clk1     ; 0            ;
; Total number of failed paths ;       ;               ;                                  ;                                                                                                                   ;                                                                                                                   ;            ;          ; 0            ;
+------------------------------+-------+---------------+----------------------------------+-------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1S10F484C5       ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minumum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Clock Analysis Only                                   ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off clear and preset signal paths                 ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;             ;
; Do Min/Max analysis using Rise/Fall delays            ; Off                ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Use Clock Latency for PLL offset                      ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+--------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                               ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; clk1            ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+