pipemult.fit.qmsg

该源码实现了一个8*8位的乘法器

{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_MAC_RAM_PACKING" "" "Info: Finished moving registers into LUTs, I/O cells, DSP blocks, and RAM blocks" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "43 unused 3.30 27 16 0 " "Info: Number of I/O pins in group: 43 (unused VREF, 3.30 VCCIO, 27 input, 16 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "LVTTL. " "Info: I/O standards used: LVTTL." {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use unused 0 29 " "Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  29 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use unused 0 30 " "Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  30 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use unused 0 51 " "Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  51 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use unused 1 51 " "Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used --  51 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use unused 1 28 " "Info: I/O bank number 5 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used --  28 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use unused 0 29 " "Info: I/O bank number 6 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  29 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use unused 0 52 " "Info: I/O bank number 7 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  52 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use unused 0 51 " "Info: I/O bank number 8 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  51 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "9 does not use unused 0 6 " "Info: I/O bank number 9 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  6 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "10 does not use unused 0 0 " "Info: I/O bank number 10 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  0 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "11 does not use unused 0 6 " "Info: I/O bank number 11 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  6 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "12 does not use unused 0 0 " "Info: I/O bank number 12 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  0 pins available" {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "0 " "Info: Fitter placement preparation operations ending: elapsed time = 0 seconds" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "4.744 ns register memory " "Info: Estimated most critical path is register to memory delay of 4.744 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns mult:inst\|lpm_mult:lpm_mult_component\|mult_m5q:auto_generated\|mac_mult2~OBSERVABLEDATAB_REGOUT0 1 REG DSPMULT_X10_Y7_N0 16 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = DSPMULT_X10_Y7_N0; Fanout = 16; REG Node = 'mult:inst\|lpm_mult:lpm_mult_component\|mult_m5q:auto_generated\|mac_mult2~OBSERVABLEDATAB_REGOUT0'" {  } { { "E:/Quartus/pipemult/db/pipemult_cmp.qrpt" "" { Report "E:/Quartus/pipemult/db/pipemult_cmp.qrpt" Compiler "pipemult" "UNKNOWN" "V1" "E:/Quartus/pipemult/db/pipemult.quartus_db" { Floorplan "E:/Quartus/pipemult/" "" "" { mult:inst|lpm_mult:lpm_mult_component|mult_m5q:auto_generated|mac_mult2~OBSERVABLEDATAB_REGOUT0 } "NODE_NAME" } "" } } { "db/mult_m5q.tdf" "" { Text "E:/Quartus/pipemult/db/mult_m5q.tdf" 46 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.757 ns) 2.757 ns mult:inst\|lpm_mult:lpm_mult_component\|mult_m5q:auto_generated\|mac_mult2 2 COMB DSPMULT_X10_Y7_N0 16 " "Info: 2: + IC(0.000 ns) + CELL(2.757 ns) = 2.757 ns; Loc. = DSPMULT_X10_Y7_N0; Fanout = 16; COMB Node = 'mult:inst\|lpm_mult:lpm_mult_component\|mult_m5q:auto_generated\|mac_mult2'" {  } { { "E:/Quartus/pipemult/db/pipemult_cmp.qrpt" "" { Report "E:/Quartus/pipemult/db/pipemult_cmp.qrpt" Compiler "pipemult" "UNKNOWN" "V1" "E:/Quartus/pipemult/db/pipemult.quartus_db" { Floorplan "E:/Quartus/pipemult/" "" "2.757 ns" { mult:inst|lpm_mult:lpm_mult_component|mult_m5q:auto_generated|mac_mult2~OBSERVABLEDATAB_REGOUT0 mult:inst|lpm_mult:lpm_mult_component|mult_m5q:auto_generated|mac_mult2 } "NODE_NAME" } "" } } { "db/mult_m5q.tdf" "" { Text "E:/Quartus/pipemult/db/mult_m5q.tdf" 46 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.878 ns) 3.635 ns mult:inst\|lpm_mult:lpm_mult_component\|mult_m5q:auto_generated\|result\[15\] 3 COMB DSPOUT_X11_Y1_N0 1 " "Info: 3: + IC(0.000 ns) + CELL(0.878 ns) = 3.635 ns; Loc. = DSPOUT_X11_Y1_N0; Fanout = 1; COMB Node = 'mult:inst\|lpm_mult:lpm_mult_component\|mult_m5q:auto_generated\|result\[15\]'" {  } { { "E:/Quartus/pipemult/db/pipemult_cmp.qrpt" "" { Report "E:/Quartus/pipemult/db/pipemult_cmp.qrpt" Compiler "pipemult" "UNKNOWN" "V1" "E:/Quartus/pipemult/db/pipemult.quartus_db" { Floorplan "E:/Quartus/pipemult/" "" "0.878 ns" { mult:inst|lpm_mult:lpm_mult_component|mult_m5q:auto_generated|mac_mult2 mult:inst|lpm_mult:lpm_mult_component|mult_m5q:auto_generated|result[15] } "NODE_NAME" } "" } } { "db/mult_m5q.tdf" "" { Text "E:/Quartus/pipemult/db/mult_m5q.tdf" 43 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.837 ns) + CELL(0.272 ns) 4.744 ns lpm_ram_dp0:inst1\|altsyncram:altsyncram_component\|altsyncram_g691:auto_generated\|ram_block1a15~porta_datain_reg0 4 MEM M512_X4_Y8 1 " "Info: 4: + IC(0.837 ns) + CELL(0.272 ns) = 4.744 ns; Loc. = M512_X4_Y8; Fanout = 1; MEM Node = 'lpm_ram_dp0:inst1\|altsyncram:altsyncram_component\|altsyncram_g691:auto_generated\|ram_block1a15~porta_datain_reg0'" {  } { { "E:/Quartus/pipemult/db/pipemult_cmp.qrpt" "" { Report "E:/Quartus/pipemult/db/pipemult_cmp.qrpt" Compiler "pipemult" "UNKNOWN" "V1" "E:/Quartus/pipemult/db/pipemult.quartus_db" { Floorplan "E:/Quartus/pipemult/" "" "1.109 ns" { mult:inst|lpm_mult:lpm_mult_component|mult_m5q:auto_generated|result[15] lpm_ram_dp0:inst1|altsyncram:altsyncram_component|altsyncram_g691:auto_generated|ram_block1a15~porta_datain_reg0 } "NODE_NAME" } "" } } { "db/altsyncram_g691.tdf" "" { Text "E:/Quartus/pipemult/db/altsyncram_g691.tdf" 470 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.907 ns 82.36 % " "Info: Total cell delay = 3.907 ns ( 82.36 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.837 ns 17.64 % " "Info: Total interconnect delay = 0.837 ns ( 17.64 % )" {  } {  } 0}  } { { "E:/Quartus/pipemult/db/pipemult_cmp.qrpt" "" { Report "E:/Quartus/pipemult/db/pipemult_cmp.qrpt" Compiler "pipemult" "UNKNOWN" "V1" "E:/Quartus/pipemult/db/pipemult.quartus_db" { Floorplan "E:/Quartus/pipemult/" "" "4.744 ns" { mult:inst|lpm_mult:lpm_mult_component|mult_m5q:auto_generated|mac_mult2~OBSERVABLEDATAB_REGOUT0 mult:inst|lpm_mult:lpm_mult_component|mult_m5q:auto_generated|mac_mult2 mult:inst|lpm_mult:lpm_mult_component|mult_m5q:auto_generated|result[15] lpm_ram_dp0:inst1|altsyncram:altsyncram_component|altsyncram_g691:auto_generated|ram_block1a15~porta_datain_reg0 } "NODE_NAME" } "" } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_PLACER_ESTIMATED_PERCENT_ROUTING_RESOURCE_USAGE" "1 " "Info: Estimated interconnect usage is 1% of the available device resources" {  } {  } 0}