pipemult.hif

来自「该源码实现了一个8*8位的乘法器」· HIF 代码 · 共 656 行

Version 4.2 Build 178 01/19/2005 Service Pack 1 SJ Web Edition
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OFF
OFF
OFF
OFF
OFF
FV_OFF
VRSM_ON
VHSM_ON
RETIME_OFF
REMAP_OFF
0
-- Start Partition --
|
ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP
Off
ADV_NETLIST_OPT_SYNTH_GATE_RETIME
Off
STATE_MACHINE_PROCESSING
Auto
STRATIXII_OPTIMIZATION_TECHNIQUE
Balanced
CYCLONE_OPTIMIZATION_TECHNIQUE
Balanced
CYCLONEII_OPTIMIZATION_TECHNIQUE
Balanced
STRATIX_OPTIMIZATION_TECHNIQUE
Balanced
MAXII_OPTIMIZATION_TECHNIQUE
Balanced
----
-- End Partition --
# entity
pipemult
# case_insensitive
# source_file
pipemult.bdf
1143553568
23
# storage
db|pipemult.(0).cnf
db|pipemult.(0).cnf
# end
# entity
lpm_ram_dp0
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
lpm_ram_dp0.v
1143553338
7
# storage
db|pipemult.(1).cnf
db|pipemult.(1).cnf
# internal_option {
AUTO_RESOURCE_SHARING
OFF
PRESERVE_REGISTER
OFF
DUP_REG_EXTRACTION
ON
DUP_LOGIC_EXTRACTION
ON
}
# end
# entity
altsyncram
# case_insensitive
# source_file
d:|altera|quartus42sp1|libraries|megafunctions|altsyncram.tdf
1106150404
6
# storage
db|pipemult.(2).cnf
db|pipemult.(2).cnf
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
16
PARAMETER_DEC
USR
WIDTHAD_A
5
PARAMETER_DEC
USR
NUMWORDS_A
32
PARAMETER_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
16
PARAMETER_DEC
USR
WIDTHAD_B
5
PARAMETER_DEC
USR
NUMWORDS_B
32
PARAMETER_DEC
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK0
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_DEC
USR
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
USR
INIT_FILE
UNUSED
PARAMETER_UNKNOWN
DEF
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Stratix
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_g691
PARAMETER_UNKNOWN
USR
}
# used_port {
address_a
address_a
address_a
address_a
address_a
address_b
address_b
address_b
address_b
address_b
clock0
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
wren_a
}
# include_file {
d:|altera|quartus42sp1|libraries|megafunctions|stratix_ram_block.inc
1094871114
d:|altera|quartus42sp1|libraries|megafunctions|lpm_mux.inc
1094870318
d:|altera|quartus42sp1|libraries|megafunctions|lpm_decode.inc
1094870100
d:|altera|quartus42sp1|libraries|megafunctions|aglobal42.inc
1106150390
d:|altera|quartus42sp1|libraries|megafunctions|altsyncram.inc
1094868954
d:|altera|quartus42sp1|libraries|megafunctions|a_rdenreg.inc
1094867530
d:|altera|quartus42sp1|libraries|megafunctions|altrom.inc
1094868876
d:|altera|quartus42sp1|libraries|megafunctions|altram.inc
1094868838
d:|altera|quartus42sp1|libraries|megafunctions|altdpram.inc
1094868494
d:|altera|quartus42sp1|libraries|megafunctions|altqpram.inc
1094868820
}
# end
# entity
altsyncram_g691
# case_insensitive
# source_file
db|altsyncram_g691.tdf
1143553570
6
# storage
db|pipemult.(3).cnf
db|pipemult.(3).cnf
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
wren_a
data_a0
data_a1
data_a2
data_a3
data_a4
data_a5
data_a6
data_a7
data_a8
data_a9
data_a10
data_a11
data_a12
data_a13
data_a14
data_a15
address_a0
address_a1
address_a2
address_a3
address_a4
address_b0
address_b1
address_b2
address_b3
address_b4
clock0
q_b0
q_b1
q_b2
q_b3
q_b4
q_b5
q_b6
q_b7
q_b8
q_b9
q_b10
q_b11
q_b12
q_b13
q_b14
q_b15
}
# memory_file {
none
0
}
# end
# entity
mult
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
mult.v
1143550848
7
# storage
db|pipemult.(4).cnf
db|pipemult.(4).cnf
# internal_option {
AUTO_RESOURCE_SHARING
OFF
PRESERVE_REGISTER
OFF
DUP_REG_EXTRACTION
ON
DUP_LOGIC_EXTRACTION
ON
}
# end
# entity
lpm_mult
# case_insensitive
# source_file
d:|altera|quartus42sp1|libraries|megafunctions|lpm_mult.tdf
1106150416
6
# storage
db|pipemult.(5).cnf
db|pipemult.(5).cnf
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
LPM_WIDTHA
8
PARAMETER_DEC
USR
LPM_WIDTHB
8
PARAMETER_DEC
USR
LPM_WIDTHP
16
PARAMETER_DEC
USR
LPM_WIDTHR
0
PARAMETER_UNKNOWN
DEF
LPM_WIDTHS
1
PARAMETER_DEC
USR
LPM_REPRESENTATION
UNSIGNED
PARAMETER_UNKNOWN
USR
LPM_PIPELINE
1
PARAMETER_DEC
USR
LATENCY
0
PARAMETER_UNKNOWN
DEF
INPUT_A_IS_CONSTANT
NO
PARAMETER_UNKNOWN
DEF
INPUT_B_IS_CONSTANT
NO
PARAMETER_UNKNOWN
DEF
USE_EAB
OFF
PARAMETER_UNKNOWN
DEF
MAXIMIZE_SPEED
5
PARAMETER_UNKNOWN
USR
DEVICE_FAMILY
Stratix
PARAMETER_UNKNOWN
USR
CARRY_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
APEX20K_TECHNOLOGY_MAPPER
Lut
TECH_MAPPER_APEX20K
USR
DEDICATED_MULTIPLIER_CIRCUITRY
AUTO
PARAMETER_UNKNOWN
DEF
DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO
0
PARAMETER_UNKNOWN
DEF
DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO
0
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
mult_m5q
PARAMETER_UNKNOWN
USR
INPUT_A_FIXED_VALUE
Bx
PARAMETER_UNKNOWN
DEF
INPUT_B_FIXED_VALUE
Bx
PARAMETER_UNKNOWN
DEF
}
# used_port {
aclr
clken
clock
dataa
dataa
dataa
dataa
dataa
dataa
dataa
dataa
datab
datab
datab
datab
datab
datab
datab
datab
result
result
result
result
result
result
result
result
result
result
result
result
result
result
result
result
sum
}
# include_file {
d:|altera|quartus42sp1|libraries|megafunctions|aglobal42.inc
1106150390
d:|altera|quartus42sp1|libraries|megafunctions|lpm_add_sub.inc
1094869882
d:|altera|quartus42sp1|libraries|megafunctions|multcore.inc
1094870736
d:|altera|quartus42sp1|libraries|megafunctions|bypassff.inc
1094869394
d:|altera|quartus42sp1|libraries|megafunctions|altshift.inc
1094868890
}
# end
# entity
mult_m5q
# case_insensitive
# source_file
db|mult_m5q.tdf
1143553571
6
# storage
db|pipemult.(6).cnf
db|pipemult.(6).cnf
# user_parameter {
dataout_width
72
PARAMETER_UNKNOWN
DEF
}
# used_port {
dataa0
dataa1
dataa2
dataa3
dataa4
dataa5
dataa6
dataa7
datab0
datab1
datab2
datab3
datab4
datab5
datab6
datab7
clock
result0
result1
result2
result3
result4
result5
result6
result7
result8
result9
result10
result11
result12
result13
result14
result15
}
# end
# complete