📄 pipemult.map.rpt
字号:
Analysis & Synthesis report for pipemult
Tue Mar 28 21:46:12 2006
Version 4.2 Build 178 01/19/2005 Service Pack 1 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Hierarchy
5. Analysis & Synthesis Resource Utilization by Entity
6. Analysis & Synthesis Equations
7. Analysis & Synthesis Source Files Read
8. Analysis & Synthesis Resource Usage Summary
9. Analysis & Synthesis RAM Summary
10. Analysis & Synthesis DSP Block Usage Summary
11. WYSIWYG Cells
12. General Register Statistics
13. Analysis & Synthesis Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Any megafunction design, and related netlist (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only
to program PLD devices (but not masked PLD devices) from Altera. Any
other use of such megafunction design, netlist, support information,
device programming or simulation file, or any other related documentation
or information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to the
intellectual property, including patents, copyrights, trademarks, trade
secrets, or maskworks, embodied in any such megafunction design, netlist,
support information, device programming or simulation file, or any other
related documentation or information provided by Altera or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.
+----------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-----------------------------+----------------------------------------------+
; Analysis & Synthesis Status ; Successful - Tue Mar 28 21:46:12 2006 ;
; Quartus II Version ; 4.2 Build 178 01/19/2005 SP 1 SJ Web Edition ;
; Revision Name ; pipemult ;
; Top-level Entity Name ; pipemult ;
; Family ; Stratix ;
; Total logic elements ; 0 ;
; Total pins ; 44 ;
; Total virtual pins ; 0 ;
; Total memory bits ; 512 ;
; DSP block 9-bit elements ; 1 ;
; Total PLLs ; 0 ;
; Total DLLs ; 0 ;
+-----------------------------+----------------------------------------------+
+---------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+--------------------------------------------------------------------+--------------+---------------+
; Option ; Setting ; Default Value ;
+--------------------------------------------------------------------+--------------+---------------+
; Use smart compilation ; Normal ; Normal ;
; Restructure Multiplexers ; Auto ; Auto ;
; Create Debugging Nodes for IP Cores ; off ; off ;
; Preserve fewer node names ; On ; On ;
; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; VHDL Version ; VHDL93 ; VHDL93 ;
; Family name ; Stratix ; Stratix ;
; Top-level entity name ; pipemult ; pipemult ;
; State Machine Processing ; Auto ; Auto ;
; Extract Verilog State Machines ; On ; On ;
; Extract VHDL State Machines ; On ; On ;
; DSP Block Balancing ; Auto ; Auto ;
; NOT Gate Push-Back ; On ; On ;
; Power-Up Don't Care ; On ; On ;
; Remove Redundant Logic Cells ; Off ; Off ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore LCELL Buffers ; Off ; Off ;
; Ignore SOFT Buffers ; On ; On ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Optimization Technique -- Stratix/Stratix GX ; Balanced ; Balanced ;
; Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II ; 70 ; 70 ;
; Auto Carry Chains ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Remove Duplicate Logic ; On ; On ;
; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
; Perform gate-level register retiming ; Off ; Off ;
; Allow register retiming to trade off Tsu/Tco with Fmax ; On ; On ;
; Auto ROM Replacement ; On ; On ;
; Auto RAM Replacement ; On ; On ;
; Auto DSP Block Replacement ; On ; On ;
; Auto Shift Register Replacement ; On ; On ;
; Auto Clock Enable Replacement ; On ; On ;
; Allows Synchronous Control Signal Usage in Normal Mode Logic Cells ; On ; On ;
; Auto RAM Block Balancing ; On ; On ;
; Auto Resource Sharing ; Off ; Off ;
; Allow Any RAM Size For Recognition ; Off ; Off ;
; Allow Any ROM Size For Recognition ; Off ; Off ;
; Allow Any Shift Register Size For Recognition ; Off ; Off ;
; Enable M512 Memory Blocks ; On ; On ;
+--------------------------------------------------------------------+--------------+---------------+
+-----------+
; Hierarchy ;
+-----------+
pipemult
|-- mult:inst
|-- lpm_mult:lpm_mult_component
|-- mult_m5q:auto_generated
|-- lpm_ram_dp0:inst1
|-- altsyncram:altsyncram_component
|-- altsyncram_g691:auto_generated
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+-------------------------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+--------------------------------------------------------------------------------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name ;
+-------------------------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+--------------------------------------------------------------------------------------------+
; |pipemult ; 0 (0) ; 0 ; 512 ; 1 ; 1 ; 0 ; 0 ; 44 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |pipemult ;
; |lpm_ram_dp0:inst1| ; 0 (0) ; 0 ; 512 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |pipemult|lpm_ram_dp0:inst1 ;
; |altsyncram:altsyncram_component| ; 0 (0) ; 0 ; 512 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |pipemult|lpm_ram_dp0:inst1|altsyncram:altsyncram_component ;
; |altsyncram_g691:auto_generated| ; 0 (0) ; 0 ; 512 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |pipemult|lpm_ram_dp0:inst1|altsyncram:altsyncram_component|altsyncram_g691:auto_generated ;
; |mult:inst| ; 0 (0) ; 0 ; 0 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |pipemult|mult:inst ;
; |lpm_mult:lpm_mult_component| ; 0 (0) ; 0 ; 0 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |pipemult|mult:inst|lpm_mult:lpm_mult_component ;
; |mult_m5q:auto_generated| ; 0 (0) ; 0 ; 0 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |pipemult|mult:inst|lpm_mult:lpm_mult_component|mult_m5q:auto_generated ;
+-------------------------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+--------------------------------------------------------------------------------------------+
+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -