minitos.s

minitos是一个实时的嵌入式操作系统

minitos.elf:     file format elf32-littlearm

Disassembly of section .text:

01000000 <begin>:
 1000000:	e3a000d2 	mov	r0, #210	; 0xd2
 1000004:	e121f000 	msr	CPSR_c, r0
 1000008:	e59fd084 	ldr	sp, [pc, #84]	; 1000094 <mid_adr+0x4>
 100000c:	e3a000d3 	mov	r0, #211	; 0xd3
 1000010:	e121f000 	msr	CPSR_c, r0
 1000014:	e28f5064 	add	r5, pc, #100	; 0x64
 1000018:	e8952120 	ldmia	r5, {r5, r8, sp}
 100001c:	e3a04000 	mov	r4, #0	; 0x0
 1000020:	e4884004 	str	r4, [r8], #4
 1000024:	e2455001 	sub	r5, r5, #1	; 0x1
 1000028:	e3550000 	cmp	r5, #0	; 0x0
 100002c:	cafffffa 	bgt	100001c <begin+0x1c>
 1000030:	e59f2044 	ldr	r2, [pc, #44]	; 100007c <L_AT91_SF_CIDR>
 1000034:	e5922000 	ldr	r2, [r2]
 1000038:	e58f204c 	str	r2, [pc, #4c]	; 100008c <pid_adr>
 100003c:	e3a02059 	mov	r2, #89	; 0x59
 1000040:	e58f2048 	str	r2, [pc, #48]	; 1000090 <mid_adr>
 1000044:	e3a0b000 	mov	r11, #0	; 0x0
 1000048:	eb0000a1 	bl	10002d4 <init_kernel>
 100004c:	e3a00053 	mov	r0, #83	; 0x53
 1000050:	e121f000 	msr	CPSR_c, r0
 1000054:	e3a0b000 	mov	r11, #0	; 0x0
 1000058:	ea0000cc 	b	1000390 <start_kernel>

0100005c <AT91_IRQHandler>:
 100005c:	e24ee004 	sub	lr, lr, #4	; 0x4
 1000060:	e92d5fff 	stmdb	sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, lr}
 1000064:	e14f4000 	mrs	r4, SPSR
 1000068:	e92d0010 	stmdb	sp!, {r4}
 100006c:	eb000093 	bl	10002c0 <do_IRQ>
 1000070:	e8bd0010 	ldmia	sp!, {r4}
 1000074:	e161f004 	msr	SPSR_c, r4
 1000078:	e8fd9fff 	ldmia	sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, pc}^

0100007c <L_AT91_SF_CIDR>:
 100007c:	fff00000 	swinv	0x00f00000	; IMB

01000080 <startup_data>:
 1000080:	00001000 	andeq	r1, r0, r0
 1000084:	01002008 	tsteq	r0, r8
 1000088:	01006078 	tsteq	r0, r8, ror r0

0100008c <pid_adr>:
 100008c:	01002000 	tsteq	r0, r0

01000090 <mid_adr>:
 1000090:	01002004 	tsteq	r0, r4
 1000094:	01004010 	tsteq	r0, r0, lsl r0

01000098 <IRQ_Shell>:
 1000098:	e1a0c00d 	mov	r12, sp
 100009c:	e92dd800 	stmdb	sp!, {r11, r12, lr, pc}

int gTest=0;
void IRQ_Shell(void)
{
	gTest++;
 10000a0:	e59f2010 	ldr	r2, [pc, #10]	; 10000b8 <IRQ_Shell+0x20>
 10000a4:	e5923000 	ldr	r3, [r2]
 10000a8:	e24cb004 	sub	r11, r12, #4	; 0x4
 10000ac:	e2833001 	add	r3, r3, #1	; 0x1
 10000b0:	e5823000 	str	r3, [r2]
 10000b4:	e91ba800 	ldmdb	r11, {r11, sp, pc}
 10000b8:	01006018 	tsteq	r0, r8, lsl r0

010000bc <at91_mask_irq>:
 10000bc:	e1a0c00d 	mov	r12, sp
 10000c0:	e92dd800 	stmdb	sp!, {r11, r12, lr, pc}
 10000c4:	e24cb004 	sub	r11, r12, #4	; 0x4
}

#define __arch_putb(v,a)	(*(volatile unsigned char *)(a) = (v))
#define __arch_putl(v,a)	(*(volatile unsigned int  *)(a) = (v))

/*
extern struct irqdesc irq_desc[];
*/

 /* Internal Sources */
#define LevelSensitive              (0<<5)
#define EdgeTriggered               (1<<5)

 /* External Sources */
#define LowLevel                    (0<<5)
#define NegativeEdge                (1<<5)
#define HighLevel                   (2<<5)
#define PositiveEdge                (3<<5)

static unsigned char eb01_irq_prtable[32] = {
        7 << 5, /* FIQ */
        0 << 5, /* SWIRQ */
        0 << 5, /* US0IRQ */
        0 << 5, /* US1IRQ */
        1 << 5, /* TC0IRQ */
        1 << 5, /* TC1IRQ */
        1 << 5, /* TC2IRQ */
        0 << 5, /* WDIRQ */
        0 << 5, /* PIOAIRQ */
        0 << 5, /* reserved */
        0 << 5, /* reserved */
        0 << 5, /* reserved */
        0 << 5, /* reserved */
        0 << 5, /* reserved */
        0 << 5, /* reserved */
        0 << 5, /* reserved */
        1 << 5, /* IRQ0 */
	0 << 5, /* IRQ1 */
        0 << 5, /* IRQ2 */
};

static unsigned char eb01_irq_type[32] = {
        EdgeTriggered,
        EdgeTriggered,
        EdgeTriggered,
        EdgeTriggered,
        EdgeTriggered,
        EdgeTriggered,
        EdgeTriggered,
        EdgeTriggered,
        EdgeTriggered,
        EdgeTriggered,
        EdgeTriggered,
        EdgeTriggered,
        EdgeTriggered,
        EdgeTriggered,
        EdgeTriggered,
        EdgeTriggered,

        EdgeTriggered,	/* IRQ0 = neg. edge */
        EdgeTriggered,
        EdgeTriggered,
        EdgeTriggered,
        EdgeTriggered,
        EdgeTriggered,
        EdgeTriggered,
        EdgeTriggered,
        EdgeTriggered,
        EdgeTriggered,
        EdgeTriggered,
        EdgeTriggered,
        EdgeTriggered,
        EdgeTriggered,
        EdgeTriggered,
        EdgeTriggered,
};

/*
ARMword fix_int(ARMword val)
{
	ARMword ret = 0;
	if (val & (1 << 2))
		ret |= URXINT;
	if (val & (1 << 5))
		ret |= TC1OI;
	if (val & (1 << 6))
		ret |= TC2OI;
	return(ret);
}
*/



void at91_mask_irq(unsigned int irq)
{
	unsigned long mask = 1 << (irq);
 10000c8:	e3a03001 	mov	r3, #1	; 0x1
 10000cc:	e1a03013 	mov	r3, r3, lsl r0
	__arch_putl(mask, AIC_IDCR);
 10000d0:	e3e02eed 	mvn	r2, #3792	; 0xed0
 10000d4:	e502300b 	str	r3, [r2, -#11]
}	
 10000d8:	e91ba800 	ldmdb	r11, {r11, sp, pc}

010000dc <at91_unmask_irq>:
 10000dc:	e1a0c00d 	mov	r12, sp
 10000e0:	e92dd800 	stmdb	sp!, {r11, r12, lr, pc}
 10000e4:	e24cb004 	sub	r11, r12, #4	; 0x4

void at91_unmask_irq(unsigned int irq)
{
	unsigned long mask = 1 << (irq);
	__arch_putl(mask, AIC_IECR);
 10000e8:	e3a02489 	mov	r2, #-1996488704	; 0x89000000
 10000ec:	e1a029c2 	mov	r2, r2, asr #19
 10000f0:	e3a03001 	mov	r3, #1	; 0x1
 10000f4:	e1a03013 	mov	r3, r3, lsl r0
 10000f8:	e5823000 	str	r3, [r2]
}
 10000fc:	e91ba800 	ldmdb	r11, {r11, sp, pc}

01000100 <at91_mask_ack_irq>:
 1000100:	e1a0c00d 	mov	r12, sp
 1000104:	e92dd800 	stmdb	sp!, {r11, r12, lr, pc}
 1000108:	e24cb004 	sub	r11, r12, #4	; 0x4

void at91_mask_ack_irq(unsigned int irq)
{
	at91_mask_irq(irq);
 100010c:	ebffffea 	bl	10000bc <at91_mask_irq>
        __arch_putl(0, AIC_EOICR);     /* value=don't care */
 1000110:	e3e02d3b 	mvn	r2, #3776	; 0xec0
 1000114:	e3a03000 	mov	r3, #0	; 0x0
 1000118:	e502300f 	str	r3, [r2, -#15]
 100011c:	e91ba800 	ldmdb	r11, {r11, sp, pc}

01000120 <install_irqhandler>:
 1000120:	e1a0c00d 	mov	r12, sp
 1000124:	e92dd800 	stmdb	sp!, {r11, r12, lr, pc}
}



#define IRQ_VEC		0x18
#define IRQ_ADDR	0x38

void install_irqhandler(void)
{
  unsigned int * irqaddr = (unsigned int *) IRQ_ADDR;
  unsigned int * irqvec = (unsigned int *) IRQ_VEC; 
 1000128:	e3a01018 	mov	r1, #24	; 0x18
  unsigned int vec, oldvec;

  /*  
    *irqaddr = (unsigned int) AT91_IRQHandler;
  */
  
  *irqaddr = (unsigned int) IRQ_Enter;
  
  vec = ((unsigned int) irqaddr  - (unsigned int)irqvec - 0x08) | 0xe59ff000;
 100012c:	e38134e5 	orr	r3, r1, #-452984832	; 0xe5000000
 1000130:	e383389f 	orr	r3, r3, #10420224	; 0x9f0000
 1000134:	e3833a0f 	orr	r3, r3, #61440	; 0xf000
  
  oldvec = *irqvec;
  *irqvec = vec;
 1000138:	e5813000 	str	r3, [r1]
 100013c:	e24cb004 	sub	r11, r12, #4	; 0x4
 1000140:	e59f2008 	ldr	r2, [pc, #8]	; 1000150 <install_irqhandler+0x30>
 1000144:	e3a03038 	mov	r3, #56	; 0x38
 1000148:	e5832000 	str	r2, [r3]
			
}
 100014c:	e91ba800 	ldmdb	r11, {r11, sp, pc}
 1000150:	01000440 	tsteq	r0, r0, asr #8

01000154 <init_timer>:
 1000154:	e1a0c00d 	mov	r12, sp
 1000158:	e92dd810 	stmdb	sp!, {r4, r11, r12, lr, pc}
 100015c:	e24cb004 	sub	r11, r12, #4	; 0x4



void init_timer(void)
{
        register volatile struct at91_timers* tt = (struct at91_timers*) (AT91_TC_BASE);
 1000160:	e3a01102 	mov	r1, #-2147483648	; 0x80000000
 1000164:	e1a01741 	mov	r1, r1, asr #14
        register volatile struct at91_timer_channel* tc = &tt->chans[KERNEL_TIMER].ch;
        unsigned long v;

        /* chy 2002-12-12, init sys_timer_count */
	sys_timer_count=0;
 1000168:	e3a0e000 	mov	lr, #0	; 0x0

	/* enable Kernel timer  defined in at91_init.h*/
	/* chy 2002-12-12, seems no use??? */
	HW_AT91_TIMER_INIT(KERNEL_TIMER)

        /* No SYNC */
        tt->bcr = 0;
        /* program NO signal on XC1 */
        v = tt->bmr;
	v &= ~TCNXCNS(KERNEL_TIMER,3);
	v |= TCNXCNS(KERNEL_TIMER,1);
        tt->bmr = v;

        tc->ccr = 2;  /* disable the channel */

        /* select ACLK/128 as inupt frequency for TC1 and enable CPCTRG */
        tc->cmr = 3 | (1 << 14);
 100016c:	e3a00901 	mov	r0, #16384	; 0x4000
 1000170:	e581e0c0 	str	lr, [r1, #192]
 1000174:	e2800003 	add	r0, r0, #3	; 0x3
 1000178:	e59f3058 	ldr	r3, [pc, #58]	; 10001d8 <init_timer+0x84>
	
        tc->idr = ~0ul;  /* disable all interrupt */
	tc->rc = ((ARM_CLK/128)/HZ - 1);   /* load the count limit into the CR register */
 100017c:	e3a0ce9f 	mov	r12, #2544	; 0x9f0
 1000180:	e59120c4 	ldr	r2, [r1, #196]
 1000184:	e28cc00f 	add	r12, r12, #15	; 0xf
 1000188:	e583e000 	str	lr, [r3]
 100018c:	e3c2200c 	bic	r2, r2, #12	; 0xc
 1000190:	e3822004 	orr	r2, r2, #4	; 0x4
 1000194:	e58120c4 	str	r2, [r1, #196]
 1000198:	e3a03002 	mov	r3, #2	; 0x2
 100019c:	e5813040 	str	r3, [r1, #64]
 10001a0:	e2812040 	add	r2, r1, #64	; 0x40
 10001a4:	e5820004 	str	r0, [r2, #4]
 10001a8:	e2433003 	sub	r3, r3, #3	; 0x3
 10001ac:	e5823028 	str	r3, [r2, #40]
	tc->ier = TC_CPCS;  /* enable CPCS interrupt */

	/* enable the channel */
	tc->ccr = TC_SWTRG|TC_CLKEN;
 10001b0:	e3a04005 	mov	r4, #5	; 0x5
 10001b4:	e582c01c 	str	r12, [r2, #28]
 10001b8:	e2833011 	add	r3, r3, #17	; 0x11
 10001bc:	e5823024 	str	r3, [r2, #36]
	
	/* chy 2002-12-12 no use
        gettimeoffset = atmel_gettimeoffset;
	
	timer_irq.handler = atmel_timer_interrupt;
        setup_arm_irq(KERNEL_TIMER_IRQ_NUM, &timer_irq);
        */
	at91_mask_ack_irq(KERNEL_TIMER_IRQ_NUM);
 10001c0:	e1a00004 	mov	r0, r4
 10001c4:	e5814040 	str	r4, [r1, #64]
 10001c8:	ebffffcc 	bl	1000100 <at91_mask_ack_irq>
	at91_unmask_irq(KERNEL_TIMER_IRQ_NUM);
 10001cc:	e1a00004 	mov	r0, r4
 10001d0:	ebffffc1 	bl	10000dc <at91_unmask_irq>
}
 10001d4:	e91ba810 	ldmdb	r11, {r4, r11, sp, pc}
 10001d8:	0100707c 	tsteq	r0, r12, ror r0

010001dc <atmel_timer_interrupt>:
 10001dc:	e1a0c00d 	mov	r12, sp
 10001e0:	e92dd800 	stmdb	sp!, {r11, r12, lr, pc}
 10001e4:	e24cb004 	sub	r11, r12, #4	; 0x4

void IRQ_Time(void);
void atmel_timer_interrupt(void)
{
	struct at91_timers* tt = (struct at91_timers*) (AT91_TC_BASE);
	volatile struct  at91_timer_channel* tc = &tt->chans[KERNEL_TIMER].ch;
 10001e8:	e3a03040 	mov	r3, #64	; 0x40
	//int tmp;
	unsigned long v = tc->sr; 


        sys_timer_count++;
 10001ec:	e59f1030 	ldr	r1, [pc, #30]	; 1000224 <atmel_timer_interrupt+0x48>
 10001f0:	e28334ff 	add	r3, r3, #-16777216	; 0xff000000
 10001f4:	e5912000 	ldr	r2, [r1]
 10001f8:	e28338fe 	add	r3, r3, #16646144	; 0xfe0000
 10001fc:	e5930020 	ldr	r0, [r3, #32]
 1000200:	e2822001 	add	r2, r2, #1	; 0x1
 1000204:	e5812000 	str	r2, [r1]
	
	IRQ_Time();
 1000208:	eb000355 	bl	1000f64 <IRQ_Time>
        /* end of timer interrupts */
	at91_unmask_irq(KERNEL_TIMER_IRQ_NUM);
 100020c:	e3a00005 	mov	r0, #5	; 0x5
 1000210:	ebffffb1 	bl	10000dc <at91_unmask_irq>
	__arch_putl(KERNEL_TIMER_IRQ_NUM,AIC_EOICR);
 1000214:	e3e02d3b 	mvn	r2, #3776	; 0xec0
 1000218:	e3a03005 	mov	r3, #5	; 0x5
 100021c:	e502300f 	str	r3, [r2, -#15]
}
 1000220:	e91ba800 	ldmdb	r11, {r11, sp, pc}
 1000224:	0100707c 	tsteq	r0, r12, ror r0

01000228 <at91_init_aic>:
 1000228:	e1a0c00d 	mov	r12, sp
 100022c:	e92dd800 	stmdb	sp!, {r11, r12, lr, pc}
 1000230:	e24cb004 	sub	r11, r12, #4	; 0x4


void at91_init_aic(void)
{
        int irqno;

	/* Disable all interrupts */
	__arch_putl(0xFFFFFFFF, AIC_IDCR);

        /* Clear all interrupts	*/
        __arch_putl(0xFFFFFFFF, AIC_ICCR);
        
	for ( irqno = 0 ; irqno < 32 ; irqno++ )
 1000234:	e3a01000 	mov	r1, #0	; 0x0
 1000238:	e3e02eed 	mvn	r2, #3792	; 0xed0
 100023c:	e3e03000 	mvn	r3, #0	; 0x0
 1000240:	e502300b 	str	r3, [r2, -#11]
 1000244:	e3e00d3b 	mvn	r0, #3776	; 0xec0
 1000248:	e5023007 	str	r3, [r2, -#7]
	{
	       __arch_putl(irqno, AIC_EOICR);
 100024c:	e500100f 	str	r1, [r0, -#15]
 1000250:	e2811001 	add	r1, r1, #1	; 0x1
 1000254:	e351001f 	cmp	r1, #31	; 0x1f
 1000258:	dafffffb 	ble	100024c <at91_init_aic+0x24>