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一个mips虚拟机非常好代码,使用C++来编写的,希望大家多学学,

This is a minimal MIPS64 bus module, designed for those who don't care
for anything more substantial. The TCL interface is as follows:

memory		amount of RAM  in megabytes. The RAM is  mapped at the
		addresses  [0,  {memory} *  2**20  -  1]. The  maximum
		supported value is (500)  to leave room for the device
		banks.
dev0		the boot device
dev1		the first device
dev2		the second device
dev3		the third device

The programming interface is just as simple. The interrupt map is:

	0			bus interrupt (write error)
	1			system console

Interrupts 3, 4 and 5 are available for use by other devices.

The physical memory map is:

	0			memory
	{memory} * 2**20	bus error
	0x1F400000		control registers
		   +  0		[32 bits, ro] memory size in megabytes
	           +  8		[8 bits] console data
		   + 16		[32 bits] status register (see below)
		   + 24		[32 bits] bus error address
	0x1F600000		dev3
	0x1F800000		dev2
	0x1FA00000		dev1
	0x1FC00000		dev0
	0x1FE00000		bus error

The regions marked `bus error'  cause a bus interrupt when written and
a bus error when read.

The status register has the following layout:

	bits 0..1	interrupt enable mask
	     8..9	interrupt cause bits

All of  these are  read/write.  Except for  bits 8..9, these  bits are
never  modified by the  module.  Bits  8..9 are  never cleared  by the
module  (they are  treated as  "sticky"  bits.) Setting  bits 8..9  in
software  doesn't do  anything (in  particular, it  doesn't  raise the
corresponding interrupt.)