main.cc

一个mips虚拟机非常好代码,使用C++来编写的,希望大家多学学,

#include <string.h>
#include "koala.hh"

SerialType<Koala> Koala::type(
    (Koala::ImpRev < 0x2100) ? "koala-R4600" : "koala-R4700",
    (Koala::ImpRev < 0x2100) ? "R4600 MIPS III Processor" :
    	"R4700 MIPS III Processor"
);

const char* Koala::regname[32] = {
    "$0", "at", "v0", "v1", "a0", "a1", "a2", "a3",
    "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
    "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
    "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
};

// Storage for constants in MIPS64Cpu
const MIPS64Types::VA MIPS64Cpu::reset_vector_base;
const MIPS64Types::VA MIPS64Cpu::general_vector_base;
const MIPS64Types::VA MIPS64Cpu::boot_vector_base;
const MIPS64Types::VA MIPS64Cpu::cache_error_vector_base;
const int MIPS64Cpu::reset_vector;
const int MIPS64Cpu::tlb_refill_vector;
const int MIPS64Cpu::xtlb_refill_vector;
const int MIPS64Cpu::cache_error_vector;
const int MIPS64Cpu::common_vector;

Koala::Koala(const SimArgs& args)
    : MIPS64Cpu(args)
{
    if (args.length() > 3)
	throw Error("Too many arguments to \"sim::install %s\".", type.name());
    define("bus", conf.bus);
    define("sysClockRatio", conf.ec, 2);
    define("writebackDataRate", conf.ep, "DDDD");
    define("bigEndian", conf.be, 0);
    define("traceLevel", conf.trace, 0);
}

Koala::Koala(Checkpoint& cp)
    : Serializable(cp), MIPS64Cpu(cp)
{
    assert(TODO);
}

Koala::~Koala()
{
    // There's nothing to destroy as everything is statically-allocated,
    // except for the timer interrupt, which is conviniently destroy by the
    // base Clock class.
}

void
Koala::reset(bool warm)
{
    // Clear the reserved bits of CP0 and CP1 registers
    if (!warm) {

	// Find the attached bus module.
	bus = dynamic_cast<MIPS64Bus*>(find_module(conf.bus));
	if (!bus)
	    throw Error("%#s: \"%#s\" is not a 64bit MIPS bus module.",
			name(), conf.bus);
	// Compute the Config register fields.
	int ec, ep, be, ic, dc, ib, db;

	switch (conf.ec) {
	case 2:	ec = 0; break;
	case 3:	ec = 1; break;
	case 4:	ec = 2; break;
	case 5:	ec = 3; break;
	case 6:	ec = 4; break;
	case 7:	ec = 5; break;
	case 8:	ec = 6; break;
	default:
	    throw Error("%#s: \"%d\" is not a valid system clock ratio.", 
			name(), conf.ec);
	}

	if (!strcmp(conf.ep, "DDDD"))
	    ep = 0;
	else if (!strcmp(conf.ep, "DDxDDx"))
	    ep = 1;
	else if (!strcmp(conf.ep, "DDxxDDxx"))
	    ep = 2;
	else if (!strcmp(conf.ep, "DxDxDxDx"))
	    ep = 3;
	else if (!strcmp(conf.ep, "DDxxxDDxxx"))
	    ep = 4;
	else if (!strcmp(conf.ep, "DDxxxxDDxxxx"))
	    ep = 5;
	else if (!strcmp(conf.ep, "DxxDxxDxxDxx"))
	    ep = 6;
	else if (!strcmp(conf.ep, "DDxxxxxDDxxxxx"))
	    ep = 7;
	else if (!strcmp(conf.ep, "DxxxDxxxDxxxDxxx"))
	    ep = 8;
	else {
	    throw Error("%#s: \"%#s\" is not a valid writeback data pattern.",
			name(), conf.ep);
	}

	be = (conf.be != 0);
	ic = log2_icache_size - 12;
	dc = log2_dcache_size - 12;
	ib = (icache.line_size == 32);
	db = (dcache.line_size == 32);

	memset(cp0, 0, sizeof(cp0));
	memset(cp1, 0, sizeof(cp1));
	memset(fpr, 0, sizeof(fpr));
	count_seed = now;
	cp0[Config] = (ec << Config_EC_First) |
	    (ep << Config_EP_First) |
	    (1 << 17) |
	    (be << Config_BE) |
	    (3 << 13) |
	    (ic << Config_IC_First) |
	    (dc << Config_DC_First) |
	    (ib << Config_IB) |
	    (db << Config_DB);
	cp0[PRId] = ImpRev;
	cp1[FCR0] = ImpRev;

	// Log some module information.
	log("%#s (koala)", type.descr());
	log("Imp: 0x%02X, Rev: %d.%d, %s-endian mode",
	    bits(ImpRev, 15, 8), bits(ImpRev, 7, 4), bits(ImpRev, 3, 0),
	    big_endian_mem() ? "big" : "little");
	log("%d entry fully-associative TLB", tlb_size);
	if (icache.assoc == 1)
	    log("%dKB direct-mapped L1 I-cache (%d byte cache line)",
		icache.size/KB, icache.line_size);
	else
	    log("%dKB %d-way set-associative L1 I-cache (%d byte cache line)",
		icache.size/KB, icache.assoc, icache.line_size);
	if (dcache.assoc == 1)
	    log("%dKB direct-mapped L1 D-cache (%d byte cache line)",
		dcache.size/KB, dcache.line_size);
	else
	    log("%dKB %d-way set-associative L1 D-cache (%d byte cache line)",
		dcache.size/KB, dcache.assoc, dcache.line_size);
	log("No secondary caches.");

	log("Tracing disabled.");
	trace_level = conf.trace; //no_tracing;
	nop_count = 0;
    }
    ll_bit = false;
    sync_bit = false;

    // Deliver the reset exception.
    if (warm)
	deliver_soft_reset();
    else
	deliver_cold_reset();
    process_reset();
}

void
Koala::checkpoint(Checkpoint& cp, bool parent) const
{
    if (parent)
	cp << type << ' ' << id << '\n';
    CPU::checkpoint(cp);
    
    // Save the generic CPU state.
    cp << pc << '\n';
    for (int i = 0; i < 32; i += 2)
	cp << gpr[i] << ' ' << gpr[i + 1] << '\n';
    for (int i = 0; i < 32; i += 2)
	cp << fpr[i] << ' ' << fpr[i + 1] << '\n';
    for (int i = 0; i < 32; i += 2)
	cp << read_cp0(i) << ' ' << read_cp0(i + 1) << '\n';
    cp << cp1[0] << ' ' << cp1[31] << '\n';
    cp << hi << ' ' << lo << '\n';
    cp << ll_bit << '\n';

    // Save the Koala CPU state.
    cp << events << '\n'
       << pipeline << '\n'
       << sync_bit << '\n'
       << branch_target << '\n'
       << random_seed << '\n'
       << count_seed << '\n'
       << itlb[0].vpn << ' ' << itlb[0].pa << ' ' << itlb[0].asid << '\n'
       << itlb[1].vpn << ' ' << itlb[1].pa << ' ' << itlb[1].asid << '\n'
       << lru_itlb << '\n';

    // Save the timer.
    cp << (timer ? timer->id : SerialID(0)) << '\n';

    // Save the TLB state.
    assert(TODO);

    // Save the instruction cache.
    assert(TODO);

    // Save the data cache.
    assert(TODO);

    // Phew....
}