slides.tex

一个mips虚拟机非常好代码,使用C++来编写的,希望大家多学学,

% Slides for the L4/SPARC presentation on 23 May 2000.
% by Patryk Zadarnowski, [e-mail]
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% Title

\begin{document}
\begin{slide}
	\begin{center}
		\huge
		{\dblue Sulima Hardware Simulator}\\
		\Large
		Patryk Zadarnowski\\
		\small
		\texttt{[e-mail]}\\
		\par\vfill
		\begin{figure}[htb]
	  	\begin{center}
		\leavevmode
		\epsfxsize = .3\textwidth
		\epsfbox{sulima.eps}
		\end{center}
		\end{figure}
		\par\vfill
		University of New South Wales, Australia\\
	\end{center}%
	\vspace*{-.5\bigskipamount}
\end{slide}

% Overview

\begin{slide}

	\heading{Overview}

	A complete hardware simulator with the following features:

	{\headcol Goals:}

	\begin{slumerate}
	\item easy extendability
	\item portability
	\item complete support for MIPS III
	\item complete simulation of the real U4600 hardware
	\end{slumerate}

	\X{the first three achieved}
	\X{the fourth found impractical}

\end{slide}

% Outline

\begin{slide}

	\heading{Outline}

	\begin{slumerate}
	\item architecture
	\item device interface
	\item event interface
	\item scheduling
	\item checkpointing
	\item interpreter-grade CPU simulation
	\item future directions
	\end{slumerate}

\end{slide}

% 1. Architecture 

\begin{slide}

	\heading{Architecture}

	An architecture of independant modules (C++ objects)
	interfaced by and arranged at runtime using a Tcl script.

	{\headcol Module Hierarchy:}

	\begin{slitemize}
	\item {\tt BasicModule}\\
	infrastructure common to the Sulima module and
	the runtime modules, also creates a Tcl namespace under
	``{\tt sim::}''
		\begin{slitemize}
		\item {\tt Sulima}\\
		configuration and other functionality required
		implicitely. Created automatically by the Tcl
		{\tt init} function.
		\item {\tt Module}\\
		adds common Tcl interfaces {\tt install\_module},
		{\tt reset}, {\tt checkpoint} and the runtime
		and checkpointing constructors. May be easily
		extended; eg. state snooping, annotations.
		\end{slitemize}
	\end{slitemize}

\end{slide}

% 1. Architecture - cont'd

\begin{slide}

	\begin{slitemize}
	\item {\tt Module}
		\begin{slitemize}
		\item {\tt CPU}\\
		implements the RR schedular, destination for
		interrupts, asynchronous event queues and
		a clock, synchronized automatically with
		clocks in other {\tt CPU} modules.
			\begin{slitemize}
			\item {\tt MIPS64Cpu}\\
			implements a MIPS III CPU state, including
			all registers, caches and TLBs, therefore
			faciliating on-the-fly switching between
			different-grade simulators. Derived modules
			don't have to use these but must synchronize
			their state on request. For example,
			caches and TLBs are better maintained directly
			by each CPU simulator. Also interfaces with a
			{\tt MIPS64Bus}. Byte order ignored, and must be
			handled by each CPU module seperately.
				\begin{slitemize}
				\item {\tt Koala}\\
				an interpreter-based simulator of
				the R4600/R4700 CPU. Cycle-level accuracy
				possible (because single-issue), but currently
				only partially implemented due to lack of
				documentation
				\end{slitemize}
			\end{slitemize}
		\end{slitemize}
	\end{slitemize}

\end{slide}

% 1. Architecture - cont'd

\begin{slide}

	\begin{slitemize}
	\item {\tt Module}
		\begin{slitemize}
		\item {\tt MIPS64Bus}\\
		MIPS64-specific memory interface (sysctl, botched)\\
		MIPS64-specific interrupt events\\
		memory is a 64bit wide array and therefore 
		not affected by the host byte order
			\begin{slitemize}
			\item {\tt MIPS64SimpleBus}\\
			a simple bus with memory controller for
			a single region of RAM mapped at PA 0,
			four banks of devices mapped at
			fixed (high) addresses, and the system
			console. Four status registers:
			memory size (ro), console data (rw)
			interrupt mask and cause (rw)
			and bus error address (ro))
			\item {\tt GT\_64010A}\\
			incomplete
			\end{slitemize}
		\item {\tt ROM}
		\item {\tt MT48Tx2}
		\end{slitemize}
	\end{slitemize}

\end{slide}

% 1. Architecture - cont'd

\begin{slide}

	\begin{slitemize}
	\item {\tt Device}\\
		(not derived from {\tt Module}, but in practice
		all devices except for a trivial null device used
		as space fillers are implemented as modules.)
		\begin{slitemize}
		\item {\tt ROM}
		\item {\tt MT48Tx2}
		\item {\tt MIPS64SimpleBus::Registers}
		\item {\tt GT\_64010A::Registers}
		\item {\tt GT\_64010A::Null}
		\end{slitemize}
	\end{slitemize}

\end{slide}

% 2. Device Interface

\begin{slide}

	\heading{Device Interface}

	{\tt Device} is parametized on bus width. Each device implements
	two interfaces:

{\footnotesize
\begin{verbatim}
    ClockValue read(CPU& cpu, UInt64 addr, UInt64* buf, int size);
    ClockValue write(CPU& cpu, UInt64 addr, const UInt64* buf, int size);
\end{verbatim}
}

	Bus error can be extracted from the returned value using

{\footnotesize
\begin{verbatim}
    bool is_bus_error(ClockValue latency);
    ClockValue bus_latency(ClockValue latency);
\end{verbatim}
}

	(stored in the sign bit).

	{\headcol Example:}

	\X {\tt ROM}

\end{slide}

% 3. Event interface

\begin{slide}

	\heading{Asynchronous Event Queues}

	Handles asynchronous interrupts, scheduling events, 
	and anything else (eg. an event can be defined for collecting
	some kind of statistics every 1000 cycles, and added to the simulator
	without modifying any of the other modules.) Also allows devices
	to inject interrupt events into the CPU event queues.

	Implemented as a queue attached to each clock (CPU).
	After each fetch-execute cycle, the CPU is expected to
	call {\tt Clock::poll} which will invoke all pending events.

	Each event is a class derived from {\tt Event}, with {\tt
	Event::invoke} overloaded to perform the desired action.  The
	time of the event is assigned to the event on construction,
	and an event object is destroyed by {\tt Clock::poll} after
	invoking.

	{\headcol Example:}

	\X {\tt CPU::InterruptEvent}

\end{slide}