cpu.hh

一个mips虚拟机非常好代码,使用C++来编写的,希望大家多学学,

#ifndef mips64_cpu_hh_included
#define mips64_cpu_hh_included

#include <checkpoint.hh>
#include <cpu.hh>
#include <inttypes.hh>
#include <mips64/types.hh>
#include <mips64/bus.hh>
#include <serial.hh>


// Cute macros for defining VA constants. Note that this doesn't conflict with
// the VA type as the macro gets expanded only if followed by "(".

#define VA(a,b,c,d) C64(a,b,c,d)


// MIPS64Cpu contains generic 64-bit MIPS state information.  It is not the
// purpose of this class to maintain complete state of any MIPS CPU; in
// particular, MIPS64Cpu has no knowledge of the pipeline state, including the
// notorious branch-delay slots. That information must be maintained by any
// class derived from MIPS64Cpu. Note that this restricts the set of points at
// which the user may switch CPU simulator modules, but in practice, that
// restriction is already imposed by the construction of the lower-accuracy
// modules anyway.

class MIPS64Cpu
    : public virtual Serializable, public CPU, public MIPS64Types
{
public:

    // System Control Coprocessor (CP0) registers
    enum {
	Index		=  0,
	Random		=  1,
	EntryLo0	=  2,
	EntryLo1	=  3,
	Context		=  4,
	PageMask	=  5,
	Wired		=  6,
	// reserved	=  7,
	BadVAddr	=  8,
	Count		=  9,
	EntryHi		= 10,
	Compare		= 11,
	SR		= 12,
	Cause		= 13,
	EPC		= 14,
	PRId		= 15,
	Config		= 16,
	LLAddr		= 17,
	WatchLo		= 18,
	WatchHi		= 19,
	XContext	= 20,
	// reserved	= 21,
	// reserved	= 22,
	// reserved	= 23,
	// reserved	= 24,
	// reserved	= 25,
	ECC		= 26,
	CacheErr	= 27,
	TagLo		= 28,
	TagHi		= 29,
	ErrorEPC	= 30
	// reserved	= 31
    };

    // CP0 register layout. For single-bit fields, only one constant is
    // defined. For multi-bit fields, two constants are defined: one for the
    // first (least-significant) bit of the field, and one for the
    // most-significant bit.

    enum {
	// Index Register (0)
	Index_First = 0, Index_Last = 5,
	CPO_Index_P = 31,
	// Random Register (1)
	Random_First = 0, Random_Last = 5,
	// EntryLo0 (2), and EntryLo1 (3) Registers
	EntryLo_G = 0,
	EntryLo_V = 1,
	EntryLo_D = 2,
	EntryLo_C_First = 3, EntryLo_C_Last = 5,
	EntryLo_PFN_First = 6, EntryLo_PFN_Last = 29,
	// Context Register (4)
	Context_BadVPN2_First = 4, Context_BadVPN2_Last = 22,
	Context_PTEBase_First = 23, Context_PTEBase_Last = 63,
	// PageMask Register (5)
	PageMask_First = 13, CPO_PageMask_Last = 24,
	// Wired Register (6)
	Wired_First = 0, Wired_Last = 5,
	// Bad Virtual Address Register (BadVAddr) (8)
	// Count Register (9)
	// EntryHi Register (CP0 Register 10)
	EntryHi_ASID_First = 0, EntryHi_ASID_Last = 7,
	EntryHi_VPN2_First = 13, EntryHi_VPN2_Last = 61,
	EntryHi_R_First = 62, EntryHi_R_Last = 63, 
	// Compare Register (11)
	// SR Register (12)
	SR_IE  = 0,
	SR_EXL = 1,
	SR_ERL = 2,
	SR_KSU_First = 3, SR_KSU_Last = 4,
	SR_UX = 5,
	SR_SX = 6,
	SR_KX = 7,
	SR_IM0 = 8,
	SR_IM1 = 9,
	SR_IM2 = 10,
	SR_IM3 = 11,
	SR_IM4 = 12,
	SR_IM5 = 13,
	SR_IM6 = 14,
	SR_IM7 = 15,
	SR_IM_First = 8, SR_IM_Last = 15,
	SR_DE = 16,
	SR_CE = 17,
	SR_CH = 18,
	SR_SR = 20,
	SR_TS = 21,
	SR_BEV = 22,
	SR_DS_First = 16, SR_DS_Last = 24,
	SR_RE = 25,
	SR_FR = 26,
	SR_RP = 27,
	SR_CU0 = 28,
	SR_CU1 = 29,
	SR_CU2 = 30,
	SR_CU3 = 31,
	SR_CU_First = 28, SR_CU_Last = 31,
	// Cause Register (13)
	Cause_ExcCode_First = 0, Cause_ExcCode_Last = 6,
	Cause_IP0 = 8,
	Cause_IP1 = 9,
	Cause_IP2 = 10,
	Cause_IP3 = 11,
	Cause_IP4 = 12,
	Cause_IP5 = 13,
	Cause_IP6 = 14,
	Cause_IP7 = 15,
	Cause_IP_First = 8, Cause_IP_Last = 15,
	Cause_CE_First = 28, Cause_CE_Last = 29,
	Cause_BD = 31,
	// Exception Program Counter (EPC) Register (14)
	// Processor Revision Identifier (PRId) Register (15)
	CPO_PRId_Rev_First = 0, CPO_PRId_Rev_Last = 7,
	CPO_PRId_Imp_First = 8, CPO_Imp_Rev_Last = 15,
	// Config Register (16)
	Config_K0_First = 0, Config_K0_Last = 2,
	Config_CU = 3,
	Config_DB = 4,
	Config_IB = 5,
	Config_DC_First = 6, Config_DC_Last = 8,
	Config_IC_First = 9, Config_IC_Last = 11,
	Config_EB = 13,
	Config_EM = 14,
	Config_BE = 15,
	Config_SM = 16,
	Config_SC = 17,
	Config_EW_First = 18, Config_EW_Last = 19,
	Config_SW = 19,
	Config_SS = 21,
	Config_SB_First = 22, Config_SB_Last = 23,
	Config_EP_First = 24, Config_EP_Last = 27,
	Config_EC_First = 28, Config_EC_Last = 30,
	Config_CM = 31,
	// Load Linked Address (LLAddr) Register (17)
	// WatchLo (18) and WatchHi (19) Registers
	WatchLo_W = 0,
	WatchLo_R = 1,
	WatchLo_PAddr0_First = 3, WatchLo_PAddr0_Last = 31,
	WatchHi_PAddr1_First = 0, WatchHi_PAddr1_Last = 3,
	// XContext Register (20)
	XContext_BadVPN2_First = 4, XContext_BadVPN2_Last = 30, 
	XContext_R_First = 31, XContext_R_Last = 32,
	XContext_PTEBase_First = 33, XContext_PTEBase_Last = 63,
	// Error Checking and Correcting (ECC) Register (26)
	ECC_First = 0, ECC_Last = 7,
	// Cache Error (CacheErr) Register (27)
	CacheErr_PIdx_First = 0, CacheErr_PIdx_Last = 2,
	CacheErr_SIdx_First = 3, CacheErr_SIdx_Last = 21,
	CacheErr_EW = 23,
	CacheErr_EI = 24,
	CacheErr_EB = 25,
	CacheErr_EE = 26,
	CacheErr_ES = 27,
	CacheErr_ET = 28,
	CacheErr_ED = 29,
	CacheErr_EC = 30,
	CacheErr_ER = 31,
	// Cache Tag Registers [TagLo (28) and TagHi (29)]
	CacheTag_ECC_First = 0, CacheTag_ECC_Last = 6,
	CacheTag_VIndex_First = 7, CacheTag_VIndex_Last = 9,
	CacheTag_SState_First = 10, CacheTag_SState_Last = 12,
	CacheTag_STagLo_First = 13, CacheTag_STagLo_Last = 31,
	CacheTag_P = 0,
	CacheTag_PState_First = 6, CacheTag_PState_Last = 7,
	CacheTag_PTagLo_First = 8, CacheTag_PTagLo_Last = 31
	// Error Exception Program Counter (Error EPC) Register (30)
    };

    // Exception numbers.
    enum {
	EXC_Int	  =  0 << 2,	// interrupt
	EXC_Mod	  =  1 << 2,	// TLB modified exception
	EXC_TLBL  =  2 << 2,	// TLB exception (load or instruction fetch)
	EXC_TLBS  =  3 << 2,	// TLB exception (store)
	EXC_AdEL  =  4 << 2,	// Address error exception (load or fetch)
	EXC_AdES  =  5 << 2,	// Address error exception (store)
	EXC_IBE	  =  6 << 2,	// Bus error exception (instruction fetch)
	EXC_DBE	  =  7 << 2,	// Bus error exception (load or store)
	EXC_Sys	  =  8 << 2,	// Syscall exception
	EXC_Bp	  =  9 << 2,	// Breakpoint exception
	EXC_RI	  = 10 << 2,	// Reserved instruction exception
	EXC_CpU	  = 11 << 2,	// Coprocessor Unusable exception
	EXC_Ov	  = 12 << 2,	// Arithmetic overflow exception
	EXC_Tr	  = 13 << 2,	// Trap exception
	EXC_VCEI  = 14 << 2,	// Virtual Coherency Exception (I-cache)
	EXC_FPE	  = 15 << 2,	// Floating-Point exception
	// 16-22		// Reserved
	EXC_WATCH = 23 << 2,	// Reference to WatchHi/WatchLo address
	// 24-30		// Reserved
	EXC_VCED  = 31 << 2	// Virtual Coherency Exception (D-cache)
    };

    // Address space layout.
    static const VA ckseg3			= VA(FFFF,FFFF,E000,0000);
    static const VA cksseg			= VA(FFFF,FFFF,C000,0000);
    static const VA ckseg1			= VA(FFFF,FFFF,A000,0000);
    static const VA ckseg0			= VA(FFFF,FFFF,8000,0000);
    static const VA xkseg			= VA(C000,0000,0000,0000);
    static const VA xkphys			= VA(8000,0000,0000,0000);
    static const VA xksseg			= VA(4000,0000,0000,0000);
    static const VA xkuseg			= VA(0000,0000,0000,0000);

    // Exception vectors.
    static const VA reset_vector_base		= VA(FFFF,FFFF,BFC0,0000);
    static const VA general_vector_base		= VA(FFFF,FFFF,8000,0000);
    /* static const VA boot_vector_base		= VA(FFFF,FFFF,BFC0,0200); */
    static const VA boot_vector_base		= VA(FFFF,FFFF,8000,0000);
    static const VA cache_error_vector_base	= VA(FFFF,FFFF,A000,0000);

    static const int reset_vector		= 0x000;
    static const int tlb_refill_vector		= 0x000;
    static const int xtlb_refill_vector		= 0x080;
    static const int cache_error_vector		= 0x100;
    static const int common_vector		= 0x180;

    // Address decoder macros.
    int vaddr_region(VA va)
	{ return bits(va, 63, 62); }
    int vaddr_compat_region(UInt32 va)
	{ return bits(va, 31, 30); }

    // The register set.
    VA     pc;			// Program Counter
    UInt64 gpr[32];		// General Purpose Registers
    UInt64 fpr[32];		// Floating-Point General Purpose Registers
    UInt64 cp0[32];		// CP0 Registers
    UInt64 cp1[32];		// CP1 Registers
    UInt64 hi, lo;		// Multiply and Divide Registers
    bool   ll_bit;		// The Load-Linked Bit

    // Memory and data bus controller to which we are attached.
    MIPS64Bus* bus;

    // Constructors, etc.
    MIPS64Cpu(const SimArgs& args)
	: CPU(args) { }
    MIPS64Cpu(Checkpoint& cp)
	: Serializable(cp), CPU(cp) { }

    // More interrupt delivery mechanisms.
    virtual void deliver_cold_reset() = 0;
    virtual void deliver_soft_reset() = 0;
    virtual void deliver_nmi() = 0;

};

#endif // mips64_cpu_hh_included