📄 device.hh
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#ifndef device_hh_included#define device_hh_included#include <assert.hh>#include <clock.hh>#include <bus.hh>#include <cpu.hh>#include <inttypes.hh>#include <object.hh>#include <interruptsink.hh>// This header describes a generic memory-mapped device usable by any CPU.// All accesses use the host byte order for addressing. The two interfaces// return the result latency as a number of the master clock ticks. The result// has the most significant bit set if a bus error is to be signalled.// Finally, (0 < size <= 8). Note that all values of (size) in this range must// be supported.class Device : public Object{public: const int width; Bus *bus; InterruptSink *intctrl; explicit Device(int w) : width(w / 8) { bus = NULL; } virtual ClockValue read(UInt64 addr, UInt64* buf, int size) = 0; virtual ClockValue write(UInt64 addr, const UInt64* buf, int size) = 0;};// Devices signal synchronous errors through the "bus error" pin. It is// simulated by setting the sign bit of the returned latency. That way,// addition of latencies in presence of the bus error remains valid.inline bool is_bus_error(ClockValue latency){ return IntTraits<ClockValue>::Signed(latency) < 0;}inline ClockValue bus_error(ClockValue latency){ return latency | (ClockValue(1) << (8 * sizeof(ClockValue) - 1));}inline ClockValue bus_latency(ClockValue latency){ return bits(latency, int(8 * sizeof(ClockValue) - 2), 0);}#endif // device_hh_included
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