📄 escc.hh
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#ifndef escc_hh_included#define escc_hh_included#include <clock.hh>#include <checkpoint.hh>#include <cpu.hh>#include <device.hh>#include <inttypes.hh>#include <module.hh>#include <sulima.hh>#include <serial.hh>#include <simarg.hh>#include <ioqueue.hh>class ZilogESCC : public Module, public Device, public Console, public IOListener{private: static SerialType<ZilogESCC> type; // The ESCC has two channels, and two external registers per channel enum Channel { ChannelB = 0, ChannelA = 1 }; enum Register { Control = 0, Data = 1 }; // Six main interrupt sources, from lowest to highest priority enum Interrupt { ExtIntrB = 0x01, TxIntrB = 0x02, RxIntrB = 0x04, ExtIntrA = 0x08, TxIntrA = 0x10, RxIntrA = 0x20 }; // Reported Interrupt Under Service codes for each source static const UInt8 intr_ius_map[]; bool intr_enable; // Master Interrupt Enable UInt8 intr_pending; // Set of interrupts pending UInt8 intr_mask; // Set of interrupts enabled UInt8 intr_vector; // Interrupt vector UInt8 intr_ius; // Interrupt Under Service static const UInt8 rx_fifo_mask = 7; // Bitmask for size of FIFO UInt8 rx_fifo[2][8]; // Receive FIFO UInt8 rx_hi[2]; // Next character to store UInt8 rx_lo[2]; // Next character to collect UInt8 reg; // Internal register addressed unsigned int status_poll; // Number of times SR polled since last write // Check if any interrupts are pending and signal CPU void check_interrupts(void); void setup_pty(void);public: // Constructors, etc. ZilogESCC(const SimArgs& args); ZilogESCC(Checkpoint& cp); // Module interfaces. void reset(bool warm); // Serialization information. void checkpoint(Checkpoint& cp, bool parent = false) const; // Device access. ClockValue read(UInt64 addr, UInt64* buf, int size); ClockValue write(UInt64 addr, const UInt64* buf, int size); // Console void input(int c); void input(int c, int channel); void io_poll(void);private: // Configuration data. struct { int irq; int debugirq; } conf;};#endif // escc_hh_included
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