📄 write.cc
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#include <string.h>#include <assert.hh>#include <inttypes.hh>#include "rtc.hh"ClockValueMT48Tx2::write(UInt64 addr, const UInt64* buf, int size){ assert(size > 0 && size <= 8); assert(!is_power_of_two(size) || (addr & (size - 1)) == 0); // Decode the address. See also the comment in "read.cc". addr %= 2*KB; // Cache the control register in case it gets changed. UInt8 old_control = data[CONTROL]; // Store the data. UInt64 x = *buf; if (size == sizeof(UInt8)) *(UInt8 *)(data + addr) = x; else if (size == sizeof(UInt16)) *(UInt16 *)(data + addr) = x; else if (size == sizeof(UInt32)) *(UInt32 *)(data + addr) = x; else if (size == sizeof(UInt64)) *(UInt64 *)(data + addr) = x; else { // Forget about performance. if (big_endian_host()) x <<= (sizeof(x) - size) * 8; memcpy(data + addr, &x, size); } // Handle register accesses. UInt8 new_control = data[CONTROL]; if (addr + size > CONTROL) { if ((addr + size > CONTROL + 1) && !bit(old_control, 7)) msg("RTC written without halting."); if (old_control != new_control) { if (bit(old_control, 7) && !bit(new_control, 7)) update_write(bus->clock); // write bit cleared; set the clock if (!bit(old_control, 6) && bit(new_control, 6)) update_read(bus->clock); // read bit set; halt the clock } } // Compute the access latency. This chip is strictly 8-bit only, // so the overhead is paid once for every byte read. if (freq != bus->clock->freq) { read_latency = bus->clock->cycles(read_latency, freq); write_latency = bus->clock->cycles(write_latency, freq); freq = bus->clock->freq; } return write_latency * size;}
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