📄 rtc.hh
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#ifndef rtc_hh_included#define rtc_hh_included#include <clock.hh>#include <checkpoint.hh>#include <cpu.hh>#include <device.hh>#include <inttypes.hh>#include <module.hh>#include <serial.hh>#include <simarg.hh>#define USE_MMAPclass MT48Tx2 : public Module, public Device{private: static SerialType<MT48Tx2> type; // Size of the data. static const int size = 2*KB; // Configuration parameter cache. const char* file_name; ClockValue read_latency, write_latency; ClockValue initial_time; UInt8 initial_seconds; UInt8 initial_minutes; UInt8 initial_hour; UInt8 initial_weekday; UInt8 initial_date; UInt8 initial_month; UInt8 initial_year; // The clock frequency for which the cached values are valid. ClockValue freq; // Actual data array. char *data; // Register locations. enum Register { CONTROL = 0x7f8, SECONDS, MINUTES, HOUR, WEEKDAY, DATE, MONTH, YEAR }; // Update the register locations. void update_read(Clock *clock); void update_write(Clock *clock); // Load the ROM image.public: // Constructors, etc. MT48Tx2(const SimArgs& args); MT48Tx2(Checkpoint& cp); ~MT48Tx2(); // Module interfaces. void reset(bool warm); // Serialization information. void checkpoint(Checkpoint& cp, bool parent = false) const; // Device access. ClockValue read(UInt64 addr, UInt64* buf, int size); ClockValue write(UInt64 addr, const UInt64* buf, int size);private: // Conviguration data. struct { char* file_name; int read_latency, write_latency; } conf;};#endif // rtc_hh_included
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