📄 todo
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The following need to be completed.Koala:- coprocessor 1 (FPU) and related instructions- unaligned memory accesses ("unaligned.cc")- CACHE- memory latencies- correct interrupt handling in the D pipeline stage- most pipeline slips, interlocks and other stalls- second ITM slip on non-branch instructions- wasted cycle on nullified instructions- write buffers and SYNC- warning messages when entering an undefined CPU state- enable multiprocessor support (this is simple but involves further complication of the pipeline structure)Other:- implement access to the simulator state from within TCL- implement TCL annotations- there should be an ultra-fast MIPS64 JITC-based simulator somewhere
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