ethdev.constraint

此文档为采用FPGA实现的以太网MAC层

;...............................................................................
;Constraints File
;   Device  : EP1C12Q240C8
;   Board   : EthDev 1.0C
;   Project :
;
;   Created 10/3/05 - Jai Dhar
;...............................................................................

;...............................................................................
Record=FileHeader | Id=DXP Constraints v1.0
;...............................................................................


Record=Constraint | TargetKind=PCB  | TargetId=LiveDesign Evaluation Board EB2 
Record=Constraint | TargetKind=Part | TargetId=EP1C12Q240C8
Record=Constraint | TargetKind=Port | TargetId=NCSO | FPGA_PINNUM=24
Record=Constraint | TargetKind=Port | TargetId=ASDI | FPGA_PINNUM=37
Record=Constraint | TargetKind=Port | TargetId=RESET | FPGA_PINNUM=4 | FPGA_IOSTANDARD=LVTTL33

;-------------- PHY Signals ----------------
Record=Constraint | TargetKind=Port | TargetId=PHY1_COL | FPGA_PINNUM=49 | FPGA_IOSTANDARD=LVTTL33
Record=Constraint | TargetKind=Port | TargetId=PHY1_CRS | FPGA_PINNUM=48 | FPGA_IOSTANDARD=LVTTL33
Record=Constraint | TargetKind=Port | TargetId=PHY1_MDC | FPGA_PINNUM=65 | FPGA_IOSTANDARD=LVTTL33
Record=Constraint | TargetKind=Port | TargetId=PHY1_RXDV | FPGA_PINNUM=60 | FPGA_IOSTANDARD=LVTTL33
Record=Constraint | TargetKind=Port | TargetId=PHY1_TXC | FPGA_PINNUM=57 | FPGA_IOSTANDARD=LVTTL33
Record=Constraint | TargetKind=Port | TargetId=PHY1_TXEN | FPGA_PINNUM=56 | FPGA_IOSTANDARD=LVTTL33
Record=Constraint | TargetKind=Port | TargetId=PHY1_AD[4..0] | FPGA_PINNUM=75,74,73,68,67 | FPGA_IOSTANDARD=LVTTL33,LVTTL33,LVTTL33,LVTTL33,LVTTL33
Record=Constraint | TargetKind=Port | TargetId=PHY1_LED_G | FPGA_PINNUM=76 | FPGA_IOSTANDARD=LVTTL33
Record=Constraint | TargetKind=Port | TargetId=PHY1_LED_Y | FPGA_PINNUM=46 | FPGA_IOSTANDARD=LVTTL33
Record=Constraint | TargetKind=Port | TargetId=PHY1_MDIO | FPGA_PINNUM=66 | FPGA_IOSTANDARD=LVTTL33
Record=Constraint | TargetKind=Port | TargetId=PHY1_PHY_RESET | FPGA_PINNUM=47 | FPGA_IOSTANDARD=LVTTL33
Record=Constraint | TargetKind=Port | TargetId=PHY1_RXC | FPGA_PINNUM=59 | FPGA_IOSTANDARD=LVTTL33
Record=Constraint | TargetKind=Port | TargetId=PHY1_RXD[3..0] | FPGA_PINNUM=64,63,62,61 | FPGA_IOSTANDARD=LVTTL33,LVTTL33,LVTTL33,LVTTL33
Record=Constraint | TargetKind=Port | TargetId=PHY1_RXER | FPGA_PINNUM=58 | FPGA_IOSTANDARD=LVTTL33
Record=Constraint | TargetKind=Port | TargetId=PHY1_TXD[3..0] | FPGA_PINNUM=50,53,54,55 | FPGA_IOSTANDARD=LVTTL33,LVTTL33,LVTTL33,LVTTL33

;------------- GPIO ------------------------
Record=Constraint | TargetKind=Port | TargetId=GPIO[15..0] | FPGA_PINNUM=158,156,160,159,162,161,164,163,166,165,168,167,170,169,174,173 | FPGA_IOSTANDARD=LVTTL33,LVTTL33,LVTTL33,LVTTL33,LVTTL33,LVTTL33,LVTTL33,LVTTL33,LVTTL33,LVTTL33,LVTTL33,LVTTL33,LVTTL33,LVTTL33,LVTTL33,LVTTL33
Record=Constraint | TargetKind=Port | TargetId=5VIN[7..0] | FPGA_PINNUM=8,7,6,5,11,12,13,14 | FPGA_IOSTANDARD=LVTTL33,LVTTL33,LVTTL33,LVTTL33,LVTTL33,LVTTL33,LVTTL33,LVTTL33
Record=Constraint | TargetKind=Port | TargetId=PB[3..0] | FPGA_PINNUM=240,1,2,3 | FPGA_IOSTANDARD=LVTTL33,LVTTL33,LVTTL33,LVTTL33
Record=Constraint | TargetKind=Port | TargetId=5VIO[7..0] | FPGA_PINNUM=23,21,20,19,18,17,16,15
Record=Constraint | TargetKind=Port | TargetId=LED[7..0] | FPGA_PINNUM=182,181,180,179,178,177,176,175 | FPGA_IOSTANDARD=LVTTL33,LVTTL33,LVTTL33,LVTTL33,LVTTL33,LVTTL33,LVTTL33,LVTTL33

;------------- SRAM 0 ------------------------------
Record=Constraint | TargetKind=Port | TargetId=RAM0_A[17..0] | FPGA_PINNUM=183,184,185,203,202,201,200,197,225,226,227,228,233,218,217,216,215,214 | FPGA_IOSTANDARD=LVTTL33,LVTTL33,LVTTL33,LVTTL33,LVTTL33,LVTTL33,LVTTL33,LVTTL33,LVTTL33,LVTTL33,LVTTL33,LVTTL33,LVTTL33,LVTTL33,LVTTL33,LVTTL33,LVTTL33,LVTTL33
Record=Constraint | TargetKind=Port | TargetId=RAM0_BHEn | FPGA_PINNUM=187 | FPGA_IOSTANDARD=LVTTL33
Record=Constraint | TargetKind=Port | TargetId=RAM0_BLEn | FPGA_PINNUM=188 | FPGA_IOSTANDARD=LVTTL33
Record=Constraint | TargetKind=Port | TargetId=RAM0_CEn | FPGA_PINNUM=219 | FPGA_IOSTANDARD=LVTTL33
Record=Constraint | TargetKind=Port | TargetId=RAM0_WEn | FPGA_PINNUM=234 | FPGA_IOSTANDARD=LVTTL33
Record=Constraint | TargetKind=Port | TargetId=RAM0_D[15..0] | FPGA_PINNUM=193,194,195,196,213,208,207,206,235,236,237,238,239,224,223,222 | FPGA_IOSTANDARD=LVTTL33,LVTTL33,LVTTL33,LVTTL33,LVTTL33,LVTTL33,LVTTL33,LVTTL33,LVTTL33,LVTTL33,LVTTL33,LVTTL33,LVTTL33,LVTTL33,LVTTL33,LVTTL33
Record=Constraint | TargetKind=Port | TargetId=RAM0_OEn | FPGA_PINNUM=186 | FPGA_IOSTANDARD=LVTTL33

;--------------- SRAM 1 ---------------------
Record=Constraint | TargetKind=Port | TargetId=RAM1_A[17..0] | FPGA_PINNUM=113,114,115,127,128,131,132,133,108,107,106,105,104,85,84,79,82,83 | FPGA_IOSTANDARD=LVTTL33,LVTTL33,LVTTL33,LVTTL33,LVTTL33,LVTTL33,LVTTL33,LVTTL33,LVTTL33,LVTTL33,LVTTL33,LVTTL33,LVTTL33,LVTTL33,LVTTL33,LVTTL33,LVTTL33,LVTTL33
Record=Constraint | TargetKind=Port | TargetId=RAM1_BHEn | FPGA_PINNUM=117 | FPGA_IOSTANDARD=LVTTL33
Record=Constraint | TargetKind=Port | TargetId=RAM1_BLEn | FPGA_PINNUM=118 | FPGA_IOSTANDARD=LVTTL33
Record=Constraint | TargetKind=Port | TargetId=RAM1_CEn | FPGA_PINNUM=86 | FPGA_IOSTANDARD=LVTTL33
Record=Constraint | TargetKind=Port | TargetId=RAM1_D[15..0] | FPGA_PINNUM=119,120,121,122,123,124,125,126,100,99,98,95,94,93,88,87 | FPGA_IOSTANDARD=LVTTL33,LVTTL33,LVTTL33,LVTTL33,LVTTL33,LVTTL33,LVTTL33,LVTTL33,LVTTL33,LVTTL33,LVTTL33,LVTTL33,LVTTL33,LVTTL33,LVTTL33,LVTTL33
Record=Constraint | TargetKind=Port | TargetId=RAM1_OEn | FPGA_PINNUM=116 | FPGA_IOSTANDARD=LVTTL33
Record=Constraint | TargetKind=Port | TargetId=RAM1_WEn | FPGA_PINNUM=101 | FPGA_IOSTANDARD=LVTTL33

;---------------- Nexus Soft JTAG ----------------
Record=Constraint | TargetKind=Port | TargetId=SOFT_TCK | FPGA_PINNUM=136 | FPGA_IOSTANDARD=LVTTL33
Record=Constraint | TargetKind=Port | TargetId=SOFT_TDI | FPGA_PINNUM=134 | FPGA_IOSTANDARD=LVTTL33
Record=Constraint | TargetKind=Port | TargetId=SOFT_TDO | FPGA_PINNUM=137 | FPGA_IOSTANDARD=LVTTL33
Record=Constraint | TargetKind=Port | TargetId=SOFT_TMS | FPGA_PINNUM=135 | FPGA_IOSTANDARD=LVTTL33

;------------- UART -----------------
Record=Constraint | TargetKind=Port | TargetId=UART0_RX | FPGA_PINNUM=77 | FPGA_IOSTANDARD=LVTTL33
Record=Constraint | TargetKind=Port | TargetId=UART0_TX | FPGA_PINNUM=78 | FPGA_IOSTANDARD=LVTTL33

;------------ PLL (Clocks) ----------------------
Record=Constraint | TargetKind=Port | TargetId=PLL1 | FPGA_PINNUM=29 | FPGA_IOSTANDARD=LVTTL33 | FPGA_CLOCK_PIN=TRUE
Record=Constraint | TargetKind=Port | TargetId=PLL2 | FPGA_PINNUM=153 | FPGA_IOSTANDARD=LVTTL33 | FPGA_CLOCK_PIN=TRUE
Record=Constraint | TargetKind=Port | TargetId=PLL3 | FPGA_PINNUM=152 | FPGA_IOSTANDARD=LVTTL33 | FPGA_CLOCK_PIN=TRUE
Record=Constraint | TargetKind=Port | TargetId=PLL_OUT | FPGA_PINNUM=38

;------------------ I2C ----------------------
Record=Constraint | TargetKind=Port | TargetId=I2C_SCL | FPGA_PINNUM=44
Record=Constraint | TargetKind=Port | TargetId=I2C_SDA | FPGA_PINNUM=45