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来自「此文档为采用FPGA实现的以太网MAC层」· 代码 · 共 13 行

# Reading C:/Modeltech_6.0a/tcl/vsim/pref.tcl 
# //  ModelSim SE 6.0a Sep 24 2004 
# //
# //  Copyright Mentor Graphics Corporation 2004
# //              All Rights Reserved.
# //
# //  THIS WORK CONTAINS TRADE SECRET AND 
# //  PROPRIETARY INFORMATION WHICH IS THE PROPERTY
# //  OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
# //  AND IS SUBJECT TO LICENSE TERMS.
# //
#  OpenFile "D:/hw/EthDev2/fpga/rtl/ethernet/rtl/verilog/eth_top.v"