gen_clk.txt

有用的单片机程序,包括8279和E2ROM的读写

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity gen_clk is
   generic(module:integer:=5000);
    Port ( clk : in std_logic;
           carry_out : out std_logic);
end gen_clk;

architecture Behavioral of gen_clk is
signal cq1:integer range 0 to 5000000:=0;
begin
	 process(clk) is	  
	    begin
			if clk'event and clk='1' then
			    if cq1=module-1 then   cq1<=0;					 
			    else  cq1<=cq1+1;
			    end if;
			 end if;
	  end process;
	 process(cq1) is
	 begin
			if cq1<module/2 then carry_out<='0';
			else carry_out<='1';											
			end if;
	 end process;

end Behavioral;