summer.txt

有用的单片机程序,包括8279和E2ROM的读写

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--与单片机通信，MCU产生同步脉冲及控制信号控制FPGA用不同的寄存器接收数据
 --DAC可以和CPLD兼容，要求晶振为1兆
entity summer is
    Port (cs,rst,clk:in std_logic;	 --CS是与单片机什么信号相连:可能是？？？？WR
          c,b,a:in std_logic; 	--选择控制命令信号
          db:in std_logic_vector(7 downto 0);   --与单片机的P1口相连
		fudu1,fudu2:out std_logic_vector(7 downto 0);
		address1,address2:out std_logic_vector(9 downto 0)); --输出正弦相位表地址：共1024点			
end summer;

architecture Behavioral of summer is
component daccontrol is

    Port ( fudu:in std_logic_vector(7 downto 0);
           dac_fudu:out std_logic_vector(7 downto 0));
end component;

signal add1,add2:std_logic_vector(19 downto 0);
signal ph_reg1,ph_reg2:std_logic_vector(15 downto 0);	--相位增量步长：从0到20000不等
signal ph_shift:std_logic_vector(7 downto 0);  --初始相位：8位最多可移动90度
signal ph_fudu1,ph_fudu2:std_logic_vector(7 downto 0);	--幅度植：从1 到10不等
--signal f1,f2,a1,a2,q:std_logic;
begin 

--f1<='0'; f2<='0';
--a1<='0'; a2<='0';
--q<='0';
process(cs,c,b,a,db) is
 begin 
 if cs'event and cs='0'  then
      if(c='0' and b='0' and a='0') then  ph_reg1(7 downto 0)<=db;   
   elsif(c='0' and b='0' and a='1') then  ph_reg1(15 downto 8)<=db; --f1<='1';  
   elsif(c='0' and b='1' and a='0') then  ph_shift(7 downto 0)<=db; --q<='1';   
   elsif(c='0' and b='1' and a='1') then  ph_fudu1(7 downto 0)<=db; --a1<='1';
   elsif(c='1' and b='0' and a='0') then  ph_fudu2(7 downto 0)<=db; --a2<='1';       
   elsif(c='1' and b='0' and a='1') then  ph_reg2(7 downto 0)<=db;    
   elsif(c='1' and b='1' and a='0') then  ph_reg2(15 downto 8)<=db;  --f2<='1';   
   else null;
      end if;
 end if;
end process;
process(clk) is
begin
if(clk'event and clk='1') then
 if rst='0' then               --RST低电平有效
    add1<="00000000000000000000"; --第一路20位中间地址变量
    add2(19 downto 10)<='0' & '0' & ph_shift;  --第二路把相移量放在高10位
    add2(9 downto 0)<="0000000000";  --低10位不变
 elsif add2+ph_reg2>="11110100001001000000" then add2<=add2+ph_reg2-"11110100001001000000";
 elsif add1+ph_reg1>="11110100001001000000" then add1<=add1+ph_reg1-"11110100001001000000";
 else
    add1<=add1+ph_reg1;
    add2<=add2+ph_reg2;
 end if;
end if;
end process;
u0:daccontrol port map(ph_fudu1,fudu1);
u1:daccontrol port map(ph_fudu2,fudu2);
--process(f1,f2,q,a1,a2) is
--begin
--if(a1='1' and a2='1' and f1='1' and f2='1' and q='1') then
process(rst,add1,add2,ph_reg1,ph_reg2) is
begin
if rst='1' then
address1(9 downto 0)<=add1(19 downto 10);
address2(9 downto 0)<=add2(19 downto 10); 
else
address1(9 downto 0)<="0000000000";--+ ph_reg1(7 downto 0);
address2(9 downto 0)<="0000000000";--+ ph_reg2(7 downto 0); 
--f1<='0'; f2<='0';
--a1<='0'; a2<='0';
--q<='0';
--end if;
--
end if;
end process;    
end Behavioral;







 --？？？？？？？？？？？？？不知溢出后的STD—LOGIC—VECTOR会不会自动处理