📄 ad_test.txt
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--功能:CPLD对其他外围电路:ADC0809控制转换速度
entity ad_test is
Port (ECO,fclk:in std_logic; --clk是AD0809的时钟(640kHZ);fclk是p80的时钟(50MHZ)
ALE,START,OE,cclk:OUT STD_LOGIC ); --clock是AD0809的转换速度(<10kHZ),
end ad_test;
architecture Behavioral of ad_test is
component gen_clk is
generic(module:integer:=5000);
Port ( clk : in std_logic;
carry_out : out std_logic);
end component;
type states is(st0,st1,st2,st3,st4);
signal current_state,next_state:states;
signal clk:std_logic; --上升沿用来控制ADC0809的启动
begin
u0: gen_clk generic map(78) port map(fclk,clk);
cclk<=clk;
--process(fclk,clock) is
--begin
--if rising_edge(fclk) then
-- temp1<=clock;
-- temp2<=temp1;
--end if;
--end process;
--process(temp1,temp2,en) is
--begin
--if temp1='1' and temp2='0' then en<='1';
--else en<='0';
--end if;
--end process;
process(current_state,ECO) is
BEGIN
--if en_ad0809='0' then --让ADC0809有转换的时间控制在WR——EN有效期间
case(current_state) is
when st0=>ale<='0';start<='0';oe<='0';next_state<=st1; --让ADC0809始终保持数据输出
when st1=>ale<='1';start<='1';oe<='0';next_state<=st2; --此时地址已经指向下一个
when st2=>ale<='0';start<='0';oe<='0';
if eco='1' then next_state<=st2;
else next_state<=st3;
end if;
when st3=>ale<='0';start<='0';oe<='0';
if eco='0' then next_state<=st3;
else next_state<=st4;
end if;
when st4=>ale<='0';start<='0';oe<='1';
next_state<=st0;
-- if en='0' then next_state<=st4;
-- else next_state<=st5;
-- end if;
-- when st5=>ale<='0';start<='0';oe<='1';
-- if en='1' then next_state<=st5;
-- else next_state<=st0;
-- end if;
when others=>ale<='0';start<='0';oe<='0';next_state<=st0;
end case;
--else
-- ale<='0';start<='0';oe<='0';next_state<=st0;
--end if;
end process;
process(clk) is
begin
if rising_edge(clk) then current_state<=next_state;
end if;
end process;
end Behavioral;
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