dsk5510_emif.tci

MSP430与DSP接口技术3 编辑环境C语言,未试过,仅供参考

/*
 *  Copyright 2002 by Spectrum Digital Incorporated.
 *  All rights reserved.  Property of Spectrum Digital Incorporated.
 */

/*
 *  EMIF is configured as follows:
 *
 *  CE0 - 4Mbytes of SDRAM
 *  CE1 - 512Kbytes of Flash at beginning (word address 0x200000), CPLD
 *        registers in middle of space at 0x300000.
 *
 *  The SDRAM is actually 8Mbytes in total size but since the address reach
 *  of each chip enable space is only 4Mbytes it is split between CE0 and CE1.
 *  The Flash memory and CPLD registers also reside in CE1.  You can choose
 *  which type of memory you want to see by defining the memory type (MTYPE
 *  in EMIF CE1 Space Control Register 1) as either async-16 (Flash/CPLD) or
 *  SDRAM (upper half of the SDRAM).
 */

/*
 * ======== emifCfg0 ========
 * EMIF configuration settings.
 */

emifCfg0 = EMIF.create("emifCfg0");

emifCfg0.emifManualConfigure = 1;

emifCfg0.emifGcr = 0x0221;  /* EMIF Global Control Register */
                /* MEMFREQ = 01, use CPU clock / 2 on MEMCLK */
                /* WPE = 0, write posting disabled */
                /* MEMCEN = 1, enable MEMCLK on CLKMEM pin */
                /* NOHOLD = 1, don't enable HOLD requests */

emifCfg0.emifGrr = 0x0fff;  /* EMIF Global Reset Register */
                /* EMIF_RESET = 0xffff, reset EMIF */

emifCfg0.emifCe0scr1 = 0x3fff;  /* EMIF CE0 Space Control Register 1 */
                /* MTYPE = 011, SDRAM */
                /* Other bits do not apply */

emifCfg0.emifCe0scr2 = 0x5fff;  /* EMIF CE0 Space Control Register 2 */
                /* Not used with SDRAM */

emifCfg0.emifCe0scr3 = 0x0000;  /* EMIF CE0 Space Control Register 3 */
                /* Not used with SDRAM */

emifCfg0.emifCe1scr1 = 0x1038;  /* EMIF CE1 Space Control Register 1 */
                /* MTYPE = 001, async-16 */
                /* READ SETUP = 0, no read setup */
                /* READ STROBE = 14, read strobe is 14 cycles long */
                /* READ HOLD = 0, no read hold */

emifCfg0.emifCe1scr2 = 0x0038;  /* EMIF CE1 Space Control Register 2 */
                /* WRITE SETUP = 0, no read setup */
                /* WRITE STROBE = 14, write strobe is 14 cycles long */
                /* WRITE HOLD = 0, no write hold */

emifCfg0.emifCe1scr3 = 0x0000;  /* EMIF CE1 Space Control Register 3 */
                /* TIMEOUT = 0, no timeout */

emifCfg0.emifCe2scr1 = 0x1050;  /* EMIF CE2 Space Control Register 1 */
                /* MTYPE = 001, async-16 */
                /* READ SETUP = 0, no read setup */
                /* READ STROBE = 20, read strobe is 20 cycles long */
                /* READ HOLD = 0, no read hold */

emifCfg0.emifCe2scr2 = 0x0050;  /* EMIF CE2 Space Control Register 2 */
                /* WRITE SETUP = 0, no read setup */
                /* WRITE STROBE = 20, write strobe is 20 cycles long */
                /* WRITE HOLD = 0, no write hold */

emifCfg0.emifCe2scr3 = 0x0000;  /* EMIF CE2 Space Control Register 3 */
                /* TIMEOUT = 0, no timeout */

emifCfg0.emifCe3scr1 = 0x1050;  /* EMIF CE3 Space Control Register 1 */
                /* MTYPE = 001, async-16 */
                /* READ SETUP = 0, no read setup */
                /* READ STROBE = 20, read strobe is 20 cycles long */
                /* READ HOLD = 0, no read hold */

emifCfg0.emifCe3scr2 = 0x0050;  /* EMIF CE3 Space Control Register 2 */
                /* WRITE SETUP = 0, no read setup */
                /* WRITE STROBE = 20, write strobe is 20 cycles long */
                /* WRITE HOLD = 0, no write hold */

emifCfg0.emifCe3scr3 = 0x0000;  /* EMIF CE3 Space Control Register 3 */
                /* TIMEOUT = 0, no timeout */

emifCfg0.emifSdcr1 = 0x2b11;  /* EMIF SDRAM Control Register 1 */
                /* SDRAS = 5, SDRAS cycle time = 5 */
                /* SDSIZE = 0, 64 mbit part */
                /* SDWID = 1, 32 bits wide */
                /* RFEN = 1, enable refresh */
                /* TRCD = 1, active to command delay */
                /* TRP = 1, precharge time */
emifCfg0.emifSdperiodAdv = 0x0578;  /* EMIF SDRAM Refresh Period */
                /* PERIOD = 0x0578, refresh = 14usec (1400 CLKMEM cycles) */
emifCfg0.emifSdinitAdv = 0xffff;  /* EMIF SDRAM Initialization */
                /* Write triggers SDRAM initialization sequence */
emifCfg0.emifSdcr2 = 0x0535;  /* EMIF SDRAM Control Register 1 */
                /* SDACC = 1, SDRAM bus interface is 32 bits wide */
                /* TMRD = 1, Mode register set to ACTV/DCAB/REFR delay */
                /* TRAS = 3, SDRAS active time */
                /* TACTV2ACTV = 5, SDRAS to SDRAS bank activate delay */

emifCfg0.emifManualConfigure = 0;


/*
 * ======== hEMIF0 ========
 * EMIF handle, pre-init with emifCfg0
 */
hEMIF0.emifEnablePreInit = 1;
hEMIF0.emifPreInit = prog.get("emifCfg0");