📄 dsk5510_aic23.tci
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/*
* Copyright 2002 by Spectrum Digital Incorporated.
* All rights reserved. Property of Spectrum Digital Incorporated.
*/
/*
* ======== dsk5510_aic23.tci ========
*/
/*
* This script configures the McBSPs to communicate with an AIC23 codec.
* McBSP1 is used in SPI format as the control channel with clocks being
* coming from the internal sample rate generator. McBSP2 is the data
* channel. It is used in master mode using the codec's bi-directional
* DSP data format. Each sample consists of one frame with two 16-bit
* elements corresponding to left and right. Clocks and frame syncs on
* the data channel are generated by the AIC23 external to the DSP.
*/
/*
* ======== mcbspCfg1 ========
* Create a mcbsp configuration object use for the mcbsp2 talking
* to the aic23 codec. The format is SPI with 16-bit frames. All clocks
* and frame syncs are generated internally.
*/
var mcbspCfg1 = MCBSP.create("mcbspCfg1");
mcbspCfg1.mcbspManualSet = 1;
mcbspCfg1.mcbspSpcr1 = 0x1000; /* Serial Port Control Register 1 */
/* Digital loopback disabled */
/* Right justified and sign extended */
/* Clock stop mode w/no delay */
/* Dx delay enabled and Abis mode both off */
/* RINT driven by RRDY */
/* Receiver in reset */
mcbspCfg1.mcbspSpcr2 = 0x0100; /* Serial Port Control Register 2 */
/* Free bit not set */
/* XINT driven by XRDY */
/* FSGR, SRGR and Transmitter in reset */
/* XRST, RRST, FRST and GRST need to */
/* be enabled in MCBSP_start() */
mcbspCfg1.mcbspRcr1 = 0x0000; /* Receive Control Register 1 */
/* Receive not used */
mcbspCfg1.mcbspRcr2 = 0x0000; /* Receive Control Register 2 */
/* Single phase */
mcbspCfg1.mcbspXcr1 = 0x0040; /* Transmit Control Register 1 */
/* Frame length is 1 word/frame */
/* Word length is 16 bits */
mcbspCfg1.mcbspXcr2 = 0x0000; /* Transmit Control Register 2 */
/* Single phase */
mcbspCfg1.mcbspSrgr1 = 0x0063; /* Sample Rate Generator Register 1 */
/* Use internal sample rate generator at 1/100 CPU clock */
mcbspCfg1.mcbspSrgr2 = 0x2013; /* Sample Rate Generate Register 2 */
/* CLKSM = 1, use CPU clock as SRGR reference, not external */
/* FSGM = 0, generate frame sync when DXR --> XSR */
/* FPER = 20, make frame longer than 16 bits */
mcbspCfg1.mcbspMcr1 = 0x0000; /* MultiChannel Control Register 1 */
/* No multi-channel features are used */
mcbspCfg1.mcbspMcr2 = 0x0000; /* MultiChannel Control Register 2 */
/* No multi-channel features are used */
mcbspCfg1.mcbspPcr = 0x1a0a; /* Pin Control Register */
/* RIOEN = 1, receive pins as GPIO */
/* FSXM = 1, use internal SRGR for frame sync */
/* CLKXM = 1, use internal SRGR for transmit clock */
/* FSXP = 1, transmit frame sync is active low */
/* CKXP = 1, transmit data on falling edge of CLKX */
mcbspCfg1.mcbspManualSet = 0;
/*
* This configuration script file configures MCBSP2
* for 32-bit frames consisting of a 16-bit word for each of the
* left and right channels. The AIC23 is in master mode, DSP format
* and generates clocks and frame syncs externally.
*
* Generates MCBSP_Config and MCBSP_Open api's
*/
/*
* ======== mcbspCfg2 ========
* Create a mcbsp configuration object use for the mcbsp2 talking
* to the aic23 codec.
*/
var mcbspCfg2 = MCBSP.create("mcbspCfg2");
mcbspCfg2.mcbspManualSet = 1;
mcbspCfg2.mcbspSpcr1 = 0x0000; /* Serial Port Control Register 1 */
/* Digital loopback disabled */
/* Right justified and sign extended */
/* Clock stop disabled */
/* Dx enabler and Abis mode both off */
/* RINT driven by RRDY */
/* Receiver in reset */
mcbspCfg2.mcbspSpcr2 = 0x0100; /* Serial Port Control Register 2 */
/* Free bit not set */
/* XINT driven by XRDY */
/* FSGR, SRGR and Transmitter in reset */
/* XRST, RRST, FRST and GRST need to */
/* be enabled in MCBSP_start() */
mcbspCfg2.mcbspRcr1 = 0x0140; /* Receive Control Register 1 */
/* Frame length is 2 words/frame */
/* Word length is 16 bits */
mcbspCfg2.mcbspRcr2 = 0x0000; /* Receive Control Register 2 */
/* Single phase */
mcbspCfg2.mcbspXcr1 = 0x0140; /* Transmit Control Register 1 */
/* Frame length is 2 words/frame */
/* Word length is 16 bits */
mcbspCfg2.mcbspXcr2 = 0x0000; /* Transmit Control Register 2 */
/* Single phase */
mcbspCfg2.mcbspSrgr1 = 0x0000; /* Sample Rate Generator Register 1 */
/* AIC23 generates clocks externally, SRGR disabled */
mcbspCfg2.mcbspSrgr2 = 0x0000; /* Sample Rate Generate Register 2 */
/* AIC23 generates clocks externally, SRGR disabled */
mcbspCfg2.mcbspMcr1 = 0x0000; /* MultiChannel Control Register 1 */
/* No multi-channel features are used */
mcbspCfg2.mcbspMcr2 = 0x0000; /* MultiChannel Control Register 2 */
/* No multi-channel features are used */
mcbspCfg2.mcbspPcr = 0x0003; /* Pin Control Register */
/* Frame syncs triggered off internal rising edge */
/* CLKXP = 1, transmit data sampled on */
/* rising edge of CLKX */
/* CLKRP = 1, receive data sampled on */
/* rising edge of CLKR */
mcbspCfg2.mcbspManualSet = 0;
/*
* ======== McBSP1 ========
* Open McBSP handle 1 and set it to mcbspCfg1 configuration
*/
hMCBSP1.mcbspHandleEnable = 1;
hMCBSP1.mcbspHandleName = "C55XX_CONTROLHANDLE_hMcbsp";
hMCBSP1.mcbspEnablePreInit = 1;
hMCBSP1.mcbspPreInit = prog.get("mcbspCfg1");
/*
* ======== McBSP2 ========
* Open McBSP handle 2 and set it to mcbspCfg2 configuration
*/
hMCBSP2.mcbspHandleEnable = 1;
hMCBSP2.mcbspHandleName = "C55XX_DMA_MCBSP_hMcbsp";
hMCBSP2.mcbspEnablePreInit = 1;
hMCBSP2.mcbspPreInit = prog.get("mcbspCfg2");
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