postcfg_c.c

MSP430与dsp接口技术1,编辑环境C语言,我运行过,好

/*   Do *not* directly modify this file.  It was    */
/*   generated by the Configuration Tool; any  */
/*   changes risk being overwritten.                */

/* INPUT post.cdb */

/*  Include Header File  */
#include "postcfg.h"


#pragma CODE_SECTION(CSL_cfgInit,".text:CSL_cfgInit")

extern Uint16 src, dst;

/*  Config Structures */
DMA_Config dmaCfg0 = {
    0x0205,        /*  Source Destination Register (CSDP)  */
    0x5060,        /*  Control Register (CCR)  */
    0x0008,        /*  Interrupt Control Register (CICR)  */
    (DMA_AdrPtr)&src,        /*  Lower Source Address (CSSA_L) - Symbolic(Byte Address)  */
    NULL,        /*  Upper Source Address (CSSA_U) - Symbolic(Byte Address)  */
    (DMA_AdrPtr)&dst,        /*  Lower Destination Address (CDSA_L) - Symbolic(Byte Address)  */
    NULL,        /*  Upper Destination Address (CDSA_U) - Symbolic(Byte Address)  */
    0x0010,        /*  Element Number (CEN)  */
    0x0001,        /*  Frame Number (CFN)  */
    0x0000,        /*  Frame Index (CFI)  */
    0x0000         /*  Element Index (CEI)  */
};

EMIF_Config emifCfg0 = {
    0x0221,        /*  Global Control Register   */
    0xffff,        /*  Global Reset Register   */
    0x3fff,        /*  CE0 Space Control Register 1   */
    0x5fff,        /*  CE0 Space Control Register 2   */
    0x0000,        /*  CE0 Space Control Register 3   */
    0x1038,        /*  CE1 Space Control Register 1   */
    0x0038,        /*  CE1 Space Control Register 2   */
    0x0000,        /*  CE1 Space Control Register 3   */
    0x1050,        /*  CE2 Space Control Register 1   */
    0x0050,        /*  CE2 Space Control Register 2   */
    0x0000,        /*  CE2 Space Control Register 3   */
    0x1050,        /*  CE3 Space Control Register 1   */
    0x0050,        /*  CE3 Space Control Register 2   */
    0x0000,        /*  CE3 Space Control Register 3   */
    0x2b11,        /*  SDRAM Control Register 1   */
    0x0578,        /*  SDRAM Period Register   */
    0xffff,        /*  SDRAM Initialization Register   */
    0x0535         /*  SDRAM Control Register 2   */
};

MCBSP_Config mcbspCfg1 = {
    0x1000,        /*  Serial Port Control Register 1   */
    0x0100,        /*  Serial Port Control Register 2   */
    0x0000,        /*  Receive Control Register 1   */
    0x0000,        /*  Receive Control Register 2   */
    0x0040,        /*  Transmit Control Register 1   */
    0x0000,        /*  Transmit Control Register 2   */
    0x0063,        /*  Sample Rate Generator Register 1   */
    0x2013,        /*  Sample Rate Generator Register 2   */
    0x0000,        /*  Multichannel Control Register 1   */
    0x0000,        /*  Multichannel Control Register 2   */
    0x1a0a,        /*  Pin Control Register   */
    0x0000,        /*  Receive Channel Enable Register Partition A   */
    0x0000,        /*  Receive Channel Enable Register Partition B   */
    0x0000,        /*  Receive Channel Enable Register Partition C   */
    0x0000,        /*  Receive Channel Enable Register Partition D   */
    0x0000,        /*  Receive Channel Enable Register Partition E   */
    0x0000,        /*  Receive Channel Enable Register Partition F   */
    0x0000,        /*  Receive Channel Enable Register Partition G   */
    0x0000,        /*  Receive Channel Enable Register Partition H   */
    0x0000,        /*  Transmit Channel Enable Register Partition A   */
    0x0000,        /*  Transmit Channel Enable Register Partition B   */
    0x0000,        /*  Transmit Channel Enable Register Partition C   */
    0x0000,        /*  Transmit Channel Enable Register Partition D   */
    0x0000,        /*  Transmit Channel Enable Register Partition E   */
    0x0000,        /*  Transmit Channel Enable Register Partition F   */
    0x0000,        /*  Transmit Channel Enable Register Partition G   */
    0x0000         /*  Transmit Channel Enable Register Partition H   */
};

MCBSP_Config mcbspCfg2 = {
    0x0000,        /*  Serial Port Control Register 1   */
    0x0100,        /*  Serial Port Control Register 2   */
    0x0140,        /*  Receive Control Register 1   */
    0x0000,        /*  Receive Control Register 2   */
    0x0140,        /*  Transmit Control Register 1   */
    0x0000,        /*  Transmit Control Register 2   */
    0x0000,        /*  Sample Rate Generator Register 1   */
    0x0000,        /*  Sample Rate Generator Register 2   */
    0x0000,        /*  Multichannel Control Register 1   */
    0x0000,        /*  Multichannel Control Register 2   */
    0x0003,        /*  Pin Control Register   */
    0x0000,        /*  Receive Channel Enable Register Partition A   */
    0x0000,        /*  Receive Channel Enable Register Partition B   */
    0x0000,        /*  Receive Channel Enable Register Partition C   */
    0x0000,        /*  Receive Channel Enable Register Partition D   */
    0x0000,        /*  Receive Channel Enable Register Partition E   */
    0x0000,        /*  Receive Channel Enable Register Partition F   */
    0x0000,        /*  Receive Channel Enable Register Partition G   */
    0x0000,        /*  Receive Channel Enable Register Partition H   */
    0x0000,        /*  Transmit Channel Enable Register Partition A   */
    0x0000,        /*  Transmit Channel Enable Register Partition B   */
    0x0000,        /*  Transmit Channel Enable Register Partition C   */
    0x0000,        /*  Transmit Channel Enable Register Partition D   */
    0x0000,        /*  Transmit Channel Enable Register Partition E   */
    0x0000,        /*  Transmit Channel Enable Register Partition F   */
    0x0000,        /*  Transmit Channel Enable Register Partition G   */
    0x0000         /*  Transmit Channel Enable Register Partition H   */
};

MCBSP_Config mcbspCfg_loopback = {
    0xa000,        /*  Serial Port Control Register 1   */
    0x0100,        /*  Serial Port Control Register 2   */
    0x0140,        /*  Receive Control Register 1   */
    0x0000,        /*  Receive Control Register 2   */
    0x0140,        /*  Transmit Control Register 1   */
    0x0000,        /*  Transmit Control Register 2   */
    0x0000,        /*  Sample Rate Generator Register 1   */
    0x2000,        /*  Sample Rate Generator Register 2   */
    0x0000,        /*  Multichannel Control Register 1   */
    0x0000,        /*  Multichannel Control Register 2   */
    0x0a03,        /*  Pin Control Register   */
    0x0000,        /*  Receive Channel Enable Register Partition A   */
    0x0000,        /*  Receive Channel Enable Register Partition B   */
    0x0000,        /*  Receive Channel Enable Register Partition C   */
    0x0000,        /*  Receive Channel Enable Register Partition D   */
    0x0000,        /*  Receive Channel Enable Register Partition E   */
    0x0000,        /*  Receive Channel Enable Register Partition F   */
    0x0000,        /*  Receive Channel Enable Register Partition G   */
    0x0000,        /*  Receive Channel Enable Register Partition H   */
    0x0000,        /*  Transmit Channel Enable Register Partition A   */
    0x0000,        /*  Transmit Channel Enable Register Partition B   */
    0x0000,        /*  Transmit Channel Enable Register Partition C   */
    0x0000,        /*  Transmit Channel Enable Register Partition D   */
    0x0000,        /*  Transmit Channel Enable Register Partition E   */
    0x0000,        /*  Transmit Channel Enable Register Partition F   */
    0x0000,        /*  Transmit Channel Enable Register Partition G   */
    0x0000         /*  Transmit Channel Enable Register Partition H   */
};

TIMER_Config timerCfg1 = {
    0x0838,        /*  Timer Control Register (TCR)   */
    0x4e1f,        /*  Timer Period Register (PRD)   */
    0x0009         /*  Timer Prescalar Register (PRSC)   */
};

/*  Handles  */
DMA_Handle hDma0;
MCBSP_Handle hMcbsp0;
MCBSP_Handle C55XX_CONTROLHANDLE_hMcbsp;
MCBSP_Handle C55XX_DMA_MCBSP_hMcbsp;
TIMER_Handle hTimer1;

/*
 *  ======== CSL_cfgInit() ========  
 */
void CSL_cfgInit()
{
    dmaCfg0.dmacssal = (DMA_AdrPtr)(((Uint32)(&src) << 1) & 0xFFFF);
    dmaCfg0.dmacssau = (Uint16)((Uint32)(&src) >> 15);
    dmaCfg0.dmacdsal = (DMA_AdrPtr)(((Uint32)(&dst) << 1) & 0xFFFF);
    dmaCfg0.dmacdsau = (Uint16)((Uint32)(&dst) >> 15);
    hDma0 = DMA_open(DMA_CHA0, DMA_OPEN_RESET);
    hMcbsp0 = MCBSP_open(MCBSP_PORT0, MCBSP_OPEN_RESET);
    C55XX_CONTROLHANDLE_hMcbsp = MCBSP_open(MCBSP_PORT1, MCBSP_OPEN_RESET);
    C55XX_DMA_MCBSP_hMcbsp = MCBSP_open(MCBSP_PORT2, MCBSP_OPEN_RESET);
    hTimer1 = TIMER_open(TIMER_DEV1, TIMER_OPEN_RESET);
        
    DMA_config(hDma0, &dmaCfg0);
    EMIF_config(&emifCfg0);
    MCBSP_config(hMcbsp0, &mcbspCfg_loopback);
    MCBSP_config(C55XX_CONTROLHANDLE_hMcbsp, &mcbspCfg1);
    MCBSP_config(C55XX_DMA_MCBSP_hMcbsp, &mcbspCfg2);
    TIMER_config(hTimer1, &timerCfg1);

    /* You must use DMA_start() in your main code to start the DMA. */

	
    
    /* You must use MCBSP_start() in your main code to start the MCBSP. */

    
    

}