f2407.h

来自「TMS320LF2407显示子程序,将16进制转化为十进制,然后分别显示在4个L」· C头文件 代码 · 共 307 行 · 第 1/2 页

MSGID3H            .set 7219h   ;CAN message ID for mailbox 3 (upper 16 bits)
MSGCTRL3           .set 721Ah   ;CAN RTR and DLC for mailbox 3
MBX3A              .set 721Ch   ;CAN 2 of 8 bytes of mailbox 3
MBX3B              .set 721Dh   ;CAN 2 of 8 bytes of mailbox 3
MBX3C              .set 721Eh   ;CAN 2 of 8 bytes of mailbox 3
MBX3D              .set 721Fh   ;CAN 2 of 8 bytes of mailbox 3
;mailbox#4
MSGID4L            .set 7220h   ;CAN message ID for mailbox 4 (lower 16 bits)
MSGID4H            .set 7221h   ;CAN message ID for mailbox 4 (upper 16 bits)
MSGCTRL4           .set 7222h   ;CAN RTR and DLC for mailbox 4
MBX4A              .set 7224h   ;CAN 2 of 8 bytes of mailbox 4
MBX4B              .set 7225h   ;CAN 2 of 8 bytes of mailbox 4
MBX4C              .set 7226h   ;CAN 2 of 8 bytes of mailbox 4
MBX4D              .set 7227h   ;CAN 2 of 8 bytes of mailbox 4

;mailbox#5
MSGID5L            .set 7228h   ;CAN message ID for mailbox 5 (lower 16 bits)
MSGID5H            .set 7229h   ;CAN message ID for mailbox 5 (upper 16 bits)
MSGCTRL5           .set 722Ah   ;CAN RTR and DLC for mailbox 5
MBX5A              .set 722Ch   ;CAN 2 of 8 bytes of mailbox 5
MBX5B              .set 722Dh   ;CAN 2 of 8 bytes of mailbox 5
MBX5C              .set 722Eh   ;CAN 2 of 8 bytes of mailbox 5
MBX5D              .set 722Fh   ;CAN 2 of 8 bytes of mailbox 5 

;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;Event Manager A (EVA) registers
GPTCONA            .set 7400h   ;GP timer control reg A  
T1CNT              .set 7401h   ;GP timer 1 counter reg 
T1CMPR             .set 7402h   ;GP timer 1 compare reg 
T1PR               .set 7403h   ;GP timer 1 period reg 
T1CON              .set 7404h   ;GP timer 1 control reg 
T2CNT              .set 7405h   ;GP timer 2 counter reg 
T2CMPR             .set 7406h   ;GP timer 2 compare reg 
T2PR               .set 7407h   ;GP timer 2 period reg 
T2CON              .set 7408h   ;GP timer 2 control reg 
COMCONA            .set 7411h   ;Compare control reg A
ACTRA              .set 7413h   ;Compare action control reg A
DBTCONA            .set 7415h   ;Dead-band timer control reg A 
CMPR1              .set 7417h   ;compare reg 1 
CMPR2              .set 7418h   ;compare reg 2 
CMPR3              .set 7419h   ;compare reg 3 
CAPCONA            .set 7420h   ;Capture control reg A 
CAPFIFOA           .set 7422h   ;Capture FIFO status reg A 
CAP1FIFO           .set 7423h   ;Capture Channel 1 FIFO top 
CAP2FIFO           .set 7424h   ;Capture Channel 2 FIFO top 
CAP3FIFO           .set 7425h   ;Capture Channel 3 FIFO top 
CAP1FBOT           .set 7427h   ;Bottom reg of capture FIFO stack 1 
CAP2FBOT           .set 7428h   ;Bottom reg of capture FIFO stack 2 
CAP3FBOT           .set 7429h   ;Bottom reg of capture FIFO stack 3 
EVAIMRA            .set 742Ch   ;EVA interrupt mask reg A
EVAIMRB            .set 742Dh   ;EVA interrupt mask reg B
EVAIMRC            .set 742Eh   ;EVA interrupt mask reg C
EVAIFRA            .set 742Fh   ;EVA interrupt flag reg A
EVAIFRB            .set 7430h   ;EVA interrupt flag reg B
EVAIFRC            .set 7431h   ;EVA interrupt flag reg C

;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;Event Manager B (EVB) registers
GPTCONB            .set 7500h   ;GP timer control reg B 
T3CNT              .set 7501h   ;GP timer 3 counter reg
T3CMPR             .set 7502h   ;GP timer 3 compare reg
T3PR               .set 7503h   ;GP timer 3 period reg
T3CON              .set 7504h   ;GP timer 3 control reg
T4CNT              .set 7505h   ;GP timer 4 counter reg
T4CMPR             .set 7506h   ;GP timer 4 compare reg
T4PR               .set 7507h   ;GP timer 4 period reg
T4CON              .set 7508h   ;GP timer 4 control reg
COMCONB            .set 7511h   ;Compare control register B
ACTRB              .set 7513h   ;Compare action control register B
DBTCONB            .set 7515h   ;Dead-band timer control reg B
CMPR4              .set 7517h   ;Compare reg 4 
CMPR5              .set 7518h   ;Compare reg 5
CMPR6              .set 7519h   ;Compare reg 6
CAPCONB            .set 7520h   ;Capture control reg B 
CAPFIFOB           .set 7522h   ;Capture FIFO status reg B
CAP4FIFO           .set 7523h   ;Capture channel 4 FIFO top 
CAP5FIFO           .set 7524h   ;Capture channel 5 FIFO top 
CAP6FIFO           .set 7525h   ;Capture channel 6 FIFO top 
CAP4FBOT           .set 7527h   ;Bottom reg of capture FIFO stack 4 
CAP5FBOT           .set 7528h   ;Bottom reg of capture FIFO stack 5 
CAP6FBOT           .set 7529h   ;Bottom reg of capture FIFO stack 6 
EVBIMRA            .set 752Ch   ;EVB interrupt mask reg A
EVBIMRB            .set 752Dh   ;EVB interrupt mask reg B
EVBIMRC            .set 752Eh   ;EVB interrupt mask reg C
EVBIFRA            .set 752Fh   ;EVB interrupt flag reg A
EVBIFRB            .set 7530h   ;EVB interrupt flag reg B
EVBIFRC            .set 7531h   ;EVB interrupt flag reg C

;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;I/O space mapped registers
FCMR               .set 0FF0Fh  ;Flash control mode reg
WSGR               .set 0FFFFh  ;Wait-state generator reg

;************************************************
;Other useful definitions below (not addresses) *
;************************************************

;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;Data page definitions for LDP instruction
DP_B2              .set 0       ;page 0 (0000h~007Fh)
DP_B01             .set 4       ;page 4 (0200h~027Fh)
DP_B02             .set 5       ;page 5 (0280h~02FFh)
DP_B11             .set 6       ;page 6 (0300h~037Fh)
DP_B12             .set 7       ;page 7 (0380h~03FFh)
DP_SARAM1          .set 16      ;page 16(0800h~087Fh)
DP_SARAM2          .set 26      ;page 26(0D00h~0D7Fh)
DP_SARAM3          .set 18      ;page 18(0900h~097Fh)
DP_SARAM4          .set 19      ;page 19(0980h~09FFh)
DP_PF1             .set 224    ;sys regs, WD, SPI, SCI, (0x7000 - 0x707F)
DP_PF2             .set 225    ;ADC, GPIO (0x7080 - 0x70FF)
DP_CAN1            .set 226    ;CAN control regs (0x7100 - 0x717F)
DP_CAN2            .set 228    ;CAN mailboxes 1-5 (0x7200 - 0x727F)
DP_EVA             .set 232    ;Event manager A (0x7400 - 0x747F)
DP_EVB             .set 234    ;Event manager B (0x7500 - 0x757F)

;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;Bit codes for bit test instruction (BIT)
BIT15              .set 0000h  ;Bit code for testing bit 0
BIT14              .set 0001h  ;Bit code for testing bit 1
BIT13              .set 0002h  ;Bit code for testing bit 2
BIT12              .set 0003h  ;Bit code for testing bit 3
BIT11              .set 0004h  ;Bit code for testing bit 4
BIT10              .set 0005h  ;Bit code for testing bit 5
BIT9               .set 0006h  ;Bit code for testing bit 6
BIT8               .set 0007h  ;Bit code for testing bit 7
BIT7               .set 0008h  ;Bit code for testing bit 8
BIT6               .set 0009h  ;Bit code for testing bit 9
BIT5               .set 000Ah  ;Bit code for testing bit 10
BIT4               .set 000Bh  ;Bit code for testing bit 11
BIT3               .set 000Ch  ;Bit code for testing bit 12
BIT2               .set 000Dh  ;Bit code for testing bit 13
BIT1               .set 000Eh  ;Bit code for testing bit 14
BIT0               .set 000Fh  ;Bit code for testing bit 15

;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;MASK_BIT by SBIT0 and SBIT1 
B15_MSK     .set   8000h                      
B14_MSK     .set   4000                      
B13_MSK     .set   2000                      
B12_MSK     .set   1000                      
B11_MSK     .set   0800                     
B10_MSK     .set   0400                      
B9_MSK      .set   0200
B8_MSK      .set   0100
B7_MSK      .set   0080
B6_MSK      .set   0040
B5_MSK      .set   0020
B4_MSK      .set   0010
B3_MSK      .set   0008
B2_MSK      .set   0004
B1_MSK      .set   0002
B0_MSK      .set   0001