atlas.h

MIPS架构UCOS-ii移植例程

/* RTC Register B bit map definitions */
#define RTC_REGB_SET_SHF              7 
#define RTC_REGB_SET_MSK              (MSK(1) << RTC_REGB_SET_SHF)
#define RTC_REGB_SET_BIT              RTC_REGB_SET_MSK

#define RTC_REGB_PIE_SHF              6
#define RTC_REGB_PIE_MSK              (MSK(1) << RTC_REGB_PIE_SHF)
#define RTC_REGB_PIE_BIT              RTC_REGB_PIE_MSK

#define RTC_REGB_AIE_SHF              5
#define RTC_REGB_AIE_MSK              (MSK(1) << RTC_REGB_AIE_SHF)
#define RTC_REGB_AIE_BIT              RTC_REGB_AIE_MSK

#define RTC_REGB_UIE_SHF              4
#define RTC_REGB_UIE_MSK              (MSK(1) << RTC_REGB_UIE_SHF)
#define RTC_REGB_UIE_BIT              RTC_REGB_UIE_MSK

#define RTC_REGB_SQWE_SHF             3
#define RTC_REGB_SQWE_MSK             (MSK(1) << RTC_REGB_SQWE_SHF)
#define RTC_REGB_SQWE_BIT             RTC_REGB_SQWE_MSK

#define RTC_REGB_DM_SHF               2
#define RTC_REGB_DM_MSK               (MSK(1) << RTC_REGB_DM_SHF)
#define RTC_REGB_DM_BIT               RTC_REGB_DM_MSK
#define RTC_REGB_DM_BIN               1
#define RTC_REGB_DM_BCD               0

#define RTC_REGB_HF_SHF               1
#define RTC_REGB_HF_MSK               (MSK(1) << RTC_REGB_HF_SHF)
#define RTC_REGB_HF_BIT               RTC_REGB_HF_MSK
#define RTC_REGB_HF_24                1
#define RTC_REGB_HF_12                0

#define RTC_REGB_DSE_SHF              0    
#define RTC_REGB_DSE_MSK              (MSK(1) << RTC_REGB_DSE_SHF)
#define RTC_REGB_DSE_BIT              RTC_REGB_DSE_MSK


/* RTC Register C bit map definitions */
#define RTC_REGC_IRQF_SHF             7
#define RTC_REGC_IRQF_MSK             (MSK(1) << RTC_REGC_IRQF_SHF)
#define RTC_REGC_IRQF_BIT             RTC_REGC_IRQF_MSK

#define RTC_REGC_PF_SHF               6
#define RTC_REGC_PF_MSK               (MSK(1) << RTC_REGC_PF_SHF)
#define RTC_REGC_PF_BIT               RTC_REGC_PF_MSK

#define RTC_REGC_AF_SHF               5
#define RTC_REGC_AF_MSK               (MSK(1) << RTC_REGC_AF_SHF)
#define RTC_REGC_AF_BIT               RTC_REGC_AF_MSK

#define RTC_REGC_UF_SHF               4
#define RTC_REGC_UF_MSK               (MSK(1) << RTC_REGC_UF_SHF)
#define RTC_REGC_UF_BIT               RTC_REGC_UF_MSK


/* RTC Register D bit map definitions */
#define RTC_REGD_VRT_SHF              7
#define RTC_REGD_VRT_MSK              (MSK(1) << RTC_REGD_VRT_SHF)
#define RTC_REGD_VRT_BIT              RTC_REGD_VRT_MSK

#define RTC_REGD_DA_SHF               0
#define RTC_REGD_DA_MSK               (MSK(6) << RTC_REGD_DA_SHF)



/************************************************************************
 *  C code I/O Register access definitions
*************************************************************************/

#ifndef _ASSEMBLER_

#include "sysdefs.h"

#ifdef __cplusplus
extern "C" {
#endif

/* REVISION */
#define aREVISION       (KSEG1BASE+ATLAS_REVISION)
#define rREVISION       REG32(aREVISION)

/* Green LED */
#define rLEDGREEN       REG32(KSEG1(ATLAS_LEDGREEN))

/* LED BAR */
#define rLEDBAR         REG32(KSEG1(ATLAS_LEDBAR))

/* ASCII LEDs */
#define rASCIIWORD      REG32(KSEG1(ATLAS_ASCIIWORD))
#define rASCIIPOS0      REG32(KSEG1(ATLAS_ASCIIPOS0))
#define rASCIIPOS1      REG32(KSEG1(ATLAS_ASCIIPOS1))
#define rASCIIPOS2      REG32(KSEG1(ATLAS_ASCIIPOS2))
#define rASCIIPOS3      REG32(KSEG1(ATLAS_ASCIIPOS3))
#define rASCIIPOS4      REG32(KSEG1(ATLAS_ASCIIPOS4))
#define rASCIIPOS5      REG32(KSEG1(ATLAS_ASCIIPOS5))
#define rASCIIPOS6      REG32(KSEG1(ATLAS_ASCIIPOS6))
#define rASCIIPOS7      REG32(KSEG1(ATLAS_ASCIIPOS7))

/* Interrupt Controller Registers. BASE = 0x1F00.0000 */
#define rINTRAW         REG32(KSEG1(ATLAS_ICTA_BASE+0x00))
#define rINTSETEN       REG32(KSEG1(ATLAS_ICTA_BASE+0x08))
#define rINTRSTEN       REG32(KSEG1(ATLAS_ICTA_BASE+0x10))
#define rINTENABLE      REG32(KSEG1(ATLAS_ICTA_BASE+0x18))
#define rINTSTATUS      REG32(KSEG1(ATLAS_ICTA_BASE+0x20))

/* UART TI16C550 */
#define r16550RXTX      REG32(KSEG1(ATLAS_TI16C550_BASE+0x00))
#define r16550INTEN     REG32(KSEG1(ATLAS_TI16C550_BASE+0x08))
#define r16550IIFIFO    REG32(KSEG1(ATLAS_TI16C550_BASE+0x10))
#define r16550LCTRL     REG32(KSEG1(ATLAS_TI16C550_BASE+0x18))
#define r16550MCTRL     REG32(KSEG1(ATLAS_TI16C550_BASE+0x20))
#define r16550LSTAT     REG32(KSEG1(ATLAS_TI16C550_BASE+0x28))
#define r16550MSTAT     REG32(KSEG1(ATLAS_TI16C550_BASE+0x30))
#define r16550SCRATCH   REG32(KSEG1(ATLAS_TI16C550_BASE+0x38))
#define r16550DLL       REG32(KSEG1(ATLAS_TI16C550_BASE+0x00))
#define r16550DLM       REG32(KSEG1(ATLAS_TI16C550_BASE+0x08))

/* 24bit TIMER */
#define rTM0CNT         REG32(KSEG1(ATLAS_TMRA_BASE+0x00))
#define rTM0CMP         REG32(KSEG1(ATLAS_TMRA_BASE+0x08))
#define rTMINTACK       REG32(KSEG1(ATLAS_TMRA_BASE+0x20))

/* RTC */
#define rRTCADR         REG32(KSEG1(ATLAS_RTCADR))
#define rRTCDAT         REG32(KSEG1(ATLAS_RTCDAT))



/* Bit defintions */

/* rINTSETEN */
#define BIT_ICINT_SER                 (1<<0)  /* bit 0: SER */
#define BIT_ICINT_TIM0                (1<<1)  /* bit 1: TIM0 */
#define BIT_ICINT_TIM1                (1<<2)  /* bit 2: TIM1 */
#define BIT_ICINT_RTC                 (1<<4)  /* bit 4: RTC */
#define BIT_ICINT_COREHI              (1<<5)  /* bit 5: COREHI */
#define BIT_ICINT_CORELO              (1<<6)  /* bit 6: CORELO */
#define BIT_ICINT_NMI                 (1<<7)  /* bit 7: NMI */
#define BIT_ICINT_PCIA                (1<<8)  /* bit 8: PCIA */
#define BIT_ICINT_PCIB                (1<<9)  /* bit 9: PCIB */
#define BIT_ICINT_PCIC                (1<<10) /* bit 10: PCIC */
#define BIT_ICINT_PCID                (1<<11) /* bit 11: PCID */
#define BIT_ICINT_ENUM                (1<<12) /* bit 12: ENUM */
#define BIT_ICINT_DEG                 (1<<13) /* bit 13: DEG */
#define BIT_ICINT_ATXOKN              (1<<14) /* bit 14: ATXOKN */
#define BIT_ICINT_CONINTAN            (1<<15) /* bit 15: CONINTAN */
#define BIT_ICINT_CONINTBN            (1<<16) /* bit 16: CONINTBN */
#define BIT_ICINT_CONINTCN            (1<<17) /* bit 17: CONINTCN */
#define BIT_ICINT_CONINTDN            (1<<18) /* bit 18: CONINTDN */
#define BIT_ICINT_PCISERRN            (1<<19) /* bit 19: PCISERRN */



/* r16550INTEN */
#define BIT_16550RXINT                (1<<0)
#define BIT_16550TXINT                (1<<1)
#define BIT_16550LSINT                (1<<2)
#define BIT_16550MSINT                (1<<3)

#ifdef __cplusplus
}
#endif

#endif /* _ASSEMBLER_ */



/************************************************************************
 *  Assembly & C code soft vectors definition
*************************************************************************/

/* Core Exception handler vectors */
#define _ESR_STARTADDRESS 0x00000500+KSEG0BASE

#define aESR_INT            (_ESR_STARTADDRESS+0x8*EX_INT)
#define aESR_MOD            (_ESR_STARTADDRESS+0x8*EX_MOD)
#define aESR_TLBL           (_ESR_STARTADDRESS+0x8*EX_TLBL)
#define aESR_TLBS           (_ESR_STARTADDRESS+0x8*EX_TLBS)
#define aESR_ADEL           (_ESR_STARTADDRESS+0x8*EX_ADEL)
#define aESR_ADES           (_ESR_STARTADDRESS+0x8*EX_ADES)
#define aESR_IBE            (_ESR_STARTADDRESS+0x8*EX_IBE)
#define aESR_DBE            (_ESR_STARTADDRESS+0x8*EX_DBE)
#define aESR_SYS            (_ESR_STARTADDRESS+0x8*EX_SYS)
#define aESR_BP             (_ESR_STARTADDRESS+0x8*EX_BP)
#define aESR_RI             (_ESR_STARTADDRESS+0x8*EX_RI)
#define aESR_CPU            (_ESR_STARTADDRESS+0x8*EX_CPU)
#define aESR_OV             (_ESR_STARTADDRESS+0x8*EX_OV)
#define aESR_TR             (_ESR_STARTADDRESS+0x8*EX_TR)
#define aESR_FPE            (_ESR_STARTADDRESS+0x8*EX_FPE)
#define aESR_WATCH          (_ESR_STARTADDRESS+0x8*EX_WATCH)
#define aESR_MCHECK         (_ESR_STARTADDRESS+0x8*EX_MCHECK)

/* General Exception Vector */
#define aESR_EXCE           (aESR_MCHECK+0x8*1)

/* CPU Interrupt handler vectors */
#define _CPUISR_STARTADDRESS _ESR_STARTADDRESS+0x100

#define aCPUISR_SW0         (_CPUISR_STARTADDRESS+0x00)
#define aCPUISR_SW1         (_CPUISR_STARTADDRESS+0x08)
#define aCPUISR_HW0         (_CPUISR_STARTADDRESS+0x10)
#define aCPUISR_HW1         (_CPUISR_STARTADDRESS+0x18)
#define aCPUISR_HW2         (_CPUISR_STARTADDRESS+0x20)
#define aCPUISR_HW3         (_CPUISR_STARTADDRESS+0x28)
#define aCPUISR_HW4         (_CPUISR_STARTADDRESS+0x30)
#define aCPUISR_HW5         (_CPUISR_STARTADDRESS+0x38)

/* Interrupt Controller Interrupt handler vectors */
#define _ICISR_STARTADDRESS aCPUISR_HW5+0x8

#define aICISR_SER          (_ICISR_STARTADDRESS+0x00)
#define aICISR_TIM0         (_ICISR_STARTADDRESS+0x08)
#define aICISR_TIM1         (_ICISR_STARTADDRESS+0x10)
/* bit 3: reserved */
#define aICISR_RTC          (_ICISR_STARTADDRESS+0x20)
#define aICISR_COREHI       (_ICISR_STARTADDRESS+0x28)
#define aICISR_CORELO       (_ICISR_STARTADDRESS+0x30)
#define aICISR_NMI          (_ICISR_STARTADDRESS+0x38)
#define aICISR_PCIA         (_ICISR_STARTADDRESS+0x40)
#define aICISR_PCIB         (_ICISR_STARTADDRESS+0x48)
#define aICISR_PCIC         (_ICISR_STARTADDRESS+0x50)
#define aICISR_PCID         (_ICISR_STARTADDRESS+0x58)
#define aICISR_ENUM         (_ICISR_STARTADDRESS+0x60)
#define aICISR_DEG          (_ICISR_STARTADDRESS+0x68)
#define aICISR_ATXOKN       (_ICISR_STARTADDRESS+0x70)
#define aICISR_CONINTAN     (_ICISR_STARTADDRESS+0x78)
#define aICISR_CONINTBN     (_ICISR_STARTADDRESS+0x80)
#define aICISR_CONINTCN     (_ICISR_STARTADDRESS+0x88)
#define aICISR_CONINTDN     (_ICISR_STARTADDRESS+0x90)
#define aICISR_PCISERRN     (_ICISR_STARTADDRESS+0x98)

/* Interrupt Controller Interrupt handler vectors */
#define _SAAISR_STARTADDRESS aICISR_PCISERRN+0x8

#define aSAAISR_ETH         (_SAAISR_STARTADDRESS+0x00)
#define aSAAISR_UART        (_SAAISR_STARTADDRESS+0x08)



#ifndef _ASSEMBLER_

#ifdef __cplusplus
extern "C" {
#endif

/* Pointer definition for C code */
/* Core Exception handler vectors */
#define pESR_INT            (*(U32 *)aESR_INT)
#define pESR_MOD            (*(U32 *)aESR_MOD)
#define pESR_TLBL           (*(U32 *)aESR_TLBL)
#define pESR_TLBS           (*(U32 *)aESR_TLBS)
#define pESR_ADEL           (*(U32 *)aESR_ADEL)
#define pESR_ADES           (*(U32 *)aESR_ADES)
#define pESR_IBE            (*(U32 *)aESR_IBE)
#define pESR_DBE            (*(U32 *)aESR_DBE)
#define pESR_SYS            (*(U32 *)aESR_SYS)
#define pESR_BP             (*(U32 *)aESR_BP)
#define pESR_RI             (*(U32 *)aESR_RI)
#define pESR_CPU            (*(U32 *)aESR_CPU)
#define pESR_OV             (*(U32 *)aESR_OV)
#define pESR_TR             (*(U32 *)aESR_TR)
#define pESR_FPE            (*(U32 *)aESR_FPE)
#define pESR_WATCH          (*(U32 *)aESR_WATCH)
#define pESR_MCHECK         (*(U32 *)aESR_MCHECK)

/* General Exception Vector */
#define pESR_EXCE           (*(U32 *)aESR_EXCE)

/* CPU Interrupt handler vectors */
#define pCPUISR_SW0         (*(U32 *)aCPUISR_SW0)
#define pCPUISR_SW1         (*(U32 *)aCPUISR_SW1)
#define pCPUISR_HW0         (*(U32 *)aCPUISR_HW0)
#define pCPUISR_HW1         (*(U32 *)aCPUISR_HW1)
#define pCPUISR_HW2         (*(U32 *)aCPUISR_HW2)
#define pCPUISR_HW3         (*(U32 *)aCPUISR_HW3)
#define pCPUISR_HW4         (*(U32 *)aCPUISR_HW4)
#define pCPUISR_HW5         (*(U32 *)aCPUISR_HW5)

/* Interrupt Controller Interrupt handler vectors */
#define pICISR_SER          (*(U32 *)aICISR_SER)
#define pICISR_TIM0         (*(U32 *)aICISR_TIM0)
#define pICISR_TIM1         (*(U32 *)aICISR_TIM1)
/* bit 3: reserved */
#define pICISR_RTC          (*(U32 *)aICISR_RTC)
#define pICISR_COREHI       (*(U32 *)aICISR_COREHI)
#define pICISR_CORELO       (*(U32 *)aICISR_CORELO)
#define pICISR_NMI          (*(U32 *)aICISR_NMI)
#define pICISR_PCIA         (*(U32 *)aICISR_PCIA)
#define pICISR_PCIB         (*(U32 *)aICISR_PCIB)
#define pICISR_PCIC         (*(U32 *)aICISR_PCIC)
#define pICISR_PCID         (*(U32 *)aICISR_PCID)
#define pICISR_ENUM         (*(U32 *)aICISR_ENUM)
#define pICISR_DEG          (*(U32 *)aICISR_DEG)
#define pICISR_ATXOKN       (*(U32 *)aICISR_ATXOKN)
#define pICISR_CONINTAN     (*(U32 *)aICISR_CONINTAN)
#define pICISR_CONINTBN     (*(U32 *)aICISR_CONINTBN)
#define pICISR_CONINTCN     (*(U32 *)aICISR_CONINTCN)
#define pICISR_CONINTDN     (*(U32 *)aICISR_CONINTDN)
#define pICISR_PCISERRN     (*(U32 *)aICISR_PCISERRN)

#define pSAAISR_ETH         (*(U32 *)aSAAISR_ETH)
#define pSAAISR_UART        (*(U32 *)aSAAISR_UART)

#ifdef __cplusplus
}
#endif

#endif /* _ASSEMBLER_ */


/* ********************************************************************* */
/* Interface function definition */


/* ********************************************************************* */

#endif /* __ATLAS_H__ */