📄 atlas.h
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/* bit 14: ATXOKN */
#define ICTA_INTRSTEN_ATXOKN_SHF 14
#define ICTA_INTRSTEN_ATXOKN_MSK (MSK(1) << ICTA_INTRSTEN_ATXOKN_SHF)
#define ICTA_INTRSTEN_ATXOKN_SET ICTA_INTRSTEN_ATXOKN_MSK
/* bit 13: DEG */
#define ICTA_INTRSTEN_DEG_SHF 13
#define ICTA_INTRSTEN_DEG_MSK (MSK(1) << ICTA_INTRSTEN_DEG_SHF)
#define ICTA_INTRSTEN_DEG_SET ICTA_INTRSTEN_DEG_MSK
/* bit 12: ENUM */
#define ICTA_INTRSTEN_ENUM_SHF 12
#define ICTA_INTRSTEN_ENUM_MSK (MSK(1) << ICTA_INTRSTEN_ENUM_SHF)
#define ICTA_INTRSTEN_ENUM_SET ICTA_INTRSTEN_ENUM_MSK
/* bit 11: PCID */
#define ICTA_INTRSTEN_PCID_SHF 11
#define ICTA_INTRSTEN_PCID_MSK (MSK(1) << ICTA_INTRSTEN_PCID_SHF)
#define ICTA_INTRSTEN_PCID_SET ICTA_INTRSTEN_PCID_MSK
/* bit 10: PCIC */
#define ICTA_INTRSTEN_PCIC_SHF 10
#define ICTA_INTRSTEN_PCIC_MSK (MSK(1) << ICTA_INTRSTEN_PCIC_SHF)
#define ICTA_INTRSTEN_PCIC_SET ICTA_INTRSTEN_PCIC_MSK
/* bit 9: PCIB */
#define ICTA_INTRSTEN_PCIB_SHF 9
#define ICTA_INTRSTEN_PCIB_MSK (MSK(1) << ICTA_INTRSTEN_PCIB_SHF)
#define ICTA_INTRSTEN_PCIB_SET ICTA_INTRSTEN_PCIB_MSK
/* bit 8: PCIA */
#define ICTA_INTRSTEN_PCIA_SHF 8
#define ICTA_INTRSTEN_PCIA_MSK (MSK(1) << ICTA_INTRSTEN_PCIA_SHF)
#define ICTA_INTRSTEN_PCIA_SET ICTA_INTRSTEN_PCIA_MSK
/* bit 7: NMI */
#define ICTA_INTRSTEN_NMI_SHF 7
#define ICTA_INTRSTEN_NMI_MSK (MSK(1) << ICTA_INTRSTEN_NMI_SHF)
#define ICTA_INTRSTEN_NMI_SET ICTA_INTRSTEN_NMI_MSK
/* bit 6: CORELO */
#define ICTA_INTRSTEN_CORELO_SHF 6
#define ICTA_INTRSTEN_CORELO_MSK (MSK(1) << ICTA_INTRSTEN_CORELO_SHF)
#define ICTA_INTRSTEN_CORELO_SET ICTA_INTRSTEN_CORELO_MSK
/* bit 5: COREHI */
#define ICTA_INTRSTEN_COREHI_SHF 5
#define ICTA_INTRSTEN_COREHI_MSK (MSK(1) << ICTA_INTRSTEN_COREHI_SHF)
#define ICTA_INTRSTEN_COREHI_SET ICTA_INTRSTEN_COREHI_MSK
/* bit 4: RTC */
#define ICTA_INTRSTEN_RTC_SHF 4
#define ICTA_INTRSTEN_RTC_MSK (MSK(1) << ICTA_INTRSTEN_RTC_SHF)
#define ICTA_INTRSTEN_RTC_SET ICTA_INTRSTEN_RTC_MSK
/* bit 2: TIM1 */
#define ICTA_INTRSTEN_TIM1_SHF 2
#define ICTA_INTRSTEN_TIM1_MSK (MSK(1) << ICTA_INTRSTEN_TIM1_SHF)
#define ICTA_INTRSTEN_TIM1_SET ICTA_INTRSTEN_TIM1_MSK
/* bit 1: TIM0 */
#define ICTA_INTRSTEN_TIM0_SHF 1
#define ICTA_INTRSTEN_TIM0_MSK (MSK(1) << ICTA_INTRSTEN_TIM0_SHF)
#define ICTA_INTRSTEN_TIM0_SET ICTA_INTRSTEN_TIM0_MSK
/* bit 0: SER */
#define ICTA_INTRSTEN_SER_SHF 0
#define ICTA_INTRSTEN_SER_MSK (MSK(1) << ICTA_INTRSTEN_SER_SHF)
#define ICTA_INTRSTEN_SER_SET ICTA_INTRSTEN_SER_MSK
/******** reg: INTENABLE ********/
#define ICTA_INTENABLE_OFS 0x18 /* INT enable mask status */
/* bit 19: PCISERRN */
#define ICTA_INTENABLE_PCISERRN_SHF 19
#define ICTA_INTENABLE_PCISERRN_MSK (MSK(1) << ICTA_INTENABLE_PCISERRN_SHF)
#define ICTA_INTENABLE_PCISERRN_SET ICTA_INTENABLE_PCISERRN_MSK
/* bit 18: CONINTDN */
#define ICTA_INTENABLE_CONINTDN_SHF 18
#define ICTA_INTENABLE_CONINTDN_MSK (MSK(1) << ICTA_INTENABLE_CONINTDN_SHF)
#define ICTA_INTENABLE_CONINTDN_SET ICTA_INTENABLE_CONINTDN_MSK
/* bit 17: CONINTCN */
#define ICTA_INTENABLE_CONINTCN_SHF 17
#define ICTA_INTENABLE_CONINTCN_MSK (MSK(1) << ICTA_INTENABLE_CONINTCN_SHF)
#define ICTA_INTENABLE_CONINTCN_SET ICTA_INTENABLE_CONINTCN_MSK
/* bit 16: CONINTBN */
#define ICTA_INTENABLE_CONINTBN_SHF 16
#define ICTA_INTENABLE_CONINTBN_MSK (MSK(1) << ICTA_INTENABLE_CONINTBN_SHF)
#define ICTA_INTENABLE_CONINTBN_SET ICTA_INTENABLE_CONINTBN_MSK
/* bit 15: CONINTAN */
#define ICTA_INTENABLE_CONINTAN_SHF 15
#define ICTA_INTENABLE_CONINTAN_MSK (MSK(1) << ICTA_INTENABLE_CONINTAN_SHF)
#define ICTA_INTENABLE_CONINTAN_SET ICTA_INTENABLE_CONINTAN_MSK
/* bit 14: ATXOKN */
#define ICTA_INTENABLE_ATXOKN_SHF 14
#define ICTA_INTENABLE_ATXOKN_MSK (MSK(1) << ICTA_INTENABLE_ATXOKN_SHF)
#define ICTA_INTENABLE_ATXOKN_SET ICTA_INTENABLE_ATXOKN_MSK
/* bit 13: DEG */
#define ICTA_INTENABLE_DEG_SHF 13
#define ICTA_INTENABLE_DEG_MSK (MSK(1) << ICTA_INTENABLE_DEG_SHF)
#define ICTA_INTENABLE_DEG_SET ICTA_INTENABLE_DEG_MSK
/* bit 12: ENUM */
#define ICTA_INTENABLE_ENUM_SHF 12
#define ICTA_INTENABLE_ENUM_MSK (MSK(1) << ICTA_INTENABLE_ENUM_SHF)
#define ICTA_INTENABLE_ENUM_SET ICTA_INTENABLE_ENUM_MSK
/* bit 11: PCID */
#define ICTA_INTENABLE_PCID_SHF 11
#define ICTA_INTENABLE_PCID_MSK (MSK(1) << ICTA_INTENABLE_PCID_SHF)
#define ICTA_INTENABLE_PCID_SET ICTA_INTENABLE_PCID_MSK
/* bit 10: PCIC */
#define ICTA_INTENABLE_PCIC_SHF 10
#define ICTA_INTENABLE_PCIC_MSK (MSK(1) << ICTA_INTENABLE_PCIC_SHF)
#define ICTA_INTENABLE_PCIC_SET ICTA_INTENABLE_PCIC_MSK
/* bit 9: PCIB */
#define ICTA_INTENABLE_PCIB_SHF 9
#define ICTA_INTENABLE_PCIB_MSK (MSK(1) << ICTA_INTENABLE_PCIB_SHF)
#define ICTA_INTENABLE_PCIB_SET ICTA_INTENABLE_PCIB_MSK
/* bit 8: PCIA */
#define ICTA_INTENABLE_PCIA_SHF 8
#define ICTA_INTENABLE_PCIA_MSK (MSK(1) << ICTA_INTENABLE_PCIA_SHF)
#define ICTA_INTENABLE_PCIA_SET ICTA_INTENABLE_PCIA_MSK
/* bit 7: NMI */
#define ICTA_INTENABLE_NMI_SHF 7
#define ICTA_INTENABLE_NMI_MSK (MSK(1) << ICTA_INTENABLE_NMI_SHF)
#define ICTA_INTENABLE_NMI_SET ICTA_INTENABLE_NMI_MSK
/* bit 6: CORELO */
#define ICTA_INTENABLE_CORELO_SHF 6
#define ICTA_INTENABLE_CORELO_MSK (MSK(1) << ICTA_INTENABLE_CORELO_SHF)
#define ICTA_INTENABLE_CORELO_SET ICTA_INTENABLE_CORELO_MSK
/* bit 5: COREHI */
#define ICTA_INTENABLE_COREHI_SHF 5
#define ICTA_INTENABLE_COREHI_MSK (MSK(1) << ICTA_INTENABLE_COREHI_SHF)
#define ICTA_INTENABLE_COREHI_SET ICTA_INTENABLE_COREHI_MSK
/* bit 4: RTC */
#define ICTA_INTENABLE_RTC_SHF 4
#define ICTA_INTENABLE_RTC_MSK (MSK(1) << ICTA_INTENABLE_RTC_SHF)
#define ICTA_INTENABLE_RTC_SET ICTA_INTENABLE_RTC_MSK
/* bit 2: TIM1 */
#define ICTA_INTENABLE_TIM1_SHF 2
#define ICTA_INTENABLE_TIM1_MSK (MSK(1) << ICTA_INTENABLE_TIM1_SHF)
#define ICTA_INTENABLE_TIM1_SET ICTA_INTENABLE_TIM1_MSK
/* bit 1: TIM0 */
#define ICTA_INTENABLE_TIM0_SHF 1
#define ICTA_INTENABLE_TIM0_MSK (MSK(1) << ICTA_INTENABLE_TIM0_SHF)
#define ICTA_INTENABLE_TIM0_SET ICTA_INTENABLE_TIM0_MSK
/* bit 0: SER */
#define ICTA_INTENABLE_SER_SHF 0
#define ICTA_INTENABLE_SER_MSK (MSK(1) << ICTA_INTENABLE_SER_SHF)
#define ICTA_INTENABLE_SER_SET ICTA_INTENABLE_SER_MSK
/******** reg: INTSTATUS ********/
#define ICTA_INTSTATUS_OFS 0x20 /* value = INTRAW & INTENABLE */
/* bit 19: PCISERRN */
#define ICTA_INTSTATUS_PCISERRN_SHF 19
#define ICTA_INTSTATUS_PCISERRN_MSK (MSK(1) << ICTA_INTSTATUS_PCISERRN_SHF)
#define ICTA_INTSTATUS_PCISERRN_SET ICTA_INTSTATUS_PCISERRN_MSK
/* bit 18: CONINTDN */
#define ICTA_INTSTATUS_CONINTDN_SHF 18
#define ICTA_INTSTATUS_CONINTDN_MSK (MSK(1) << ICTA_INTSTATUS_CONINTDN_SHF)
#define ICTA_INTSTATUS_CONINTDN_SET ICTA_INTSTATUS_CONINTDN_MSK
/* bit 17: CONINTCN */
#define ICTA_INTSTATUS_CONINTCN_SHF 17
#define ICTA_INTSTATUS_CONINTCN_MSK (MSK(1) << ICTA_INTSTATUS_CONINTCN_SHF)
#define ICTA_INTSTATUS_CONINTCN_SET ICTA_INTSTATUS_CONINTCN_MSK
/* bit 16: CONINTBN */
#define ICTA_INTSTATUS_CONINTBN_SHF 16
#define ICTA_INTSTATUS_CONINTBN_MSK (MSK(1) << ICTA_INTSTATUS_CONINTBN_SHF)
#define ICTA_INTSTATUS_CONINTBN_SET ICTA_INTSTATUS_CONINTBN_MSK
/* bit 15: CONINTAN */
#define ICTA_INTSTATUS_CONINTAN_SHF 15
#define ICTA_INTSTATUS_CONINTAN_MSK (MSK(1) << ICTA_INTSTATUS_CONINTAN_SHF)
#define ICTA_INTSTATUS_CONINTAN_SET ICTA_INTSTATUS_CONINTAN_MSK
/* bit 14: ATXOKN */
#define ICTA_INTSTATUS_ATXOKN_SHF 14
#define ICTA_INTSTATUS_ATXOKN_MSK (MSK(1) << ICTA_INTSTATUS_ATXOKN_SHF)
#define ICTA_INTSTATUS_ATXOKN_SET ICTA_INTSTATUS_ATXOKN_MSK
/* bit 13: DEG */
#define ICTA_INTSTATUS_DEG_SHF 13
#define ICTA_INTSTATUS_DEG_MSK (MSK(1) << ICTA_INTSTATUS_DEG_SHF)
#define ICTA_INTSTATUS_DEG_SET ICTA_INTSTATUS_DEG_MSK
/* bit 12: ENUM */
#define ICTA_INTSTATUS_ENUM_SHF 12
#define ICTA_INTSTATUS_ENUM_MSK (MSK(1) << ICTA_INTSTATUS_ENUM_SHF)
#define ICTA_INTSTATUS_ENUM_SET ICTA_INTSTATUS_ENUM_MSK
/* bit 11: PCID */
#define ICTA_INTSTATUS_PCID_SHF 11
#define ICTA_INTSTATUS_PCID_MSK (MSK(1) << ICTA_INTSTATUS_PCID_SHF)
#define ICTA_INTSTATUS_PCID_SET ICTA_INTSTATUS_PCID_MSK
/* bit 10: PCIC */
#define ICTA_INTSTATUS_PCIC_SHF 10
#define ICTA_INTSTATUS_PCIC_MSK (MSK(1) << ICTA_INTSTATUS_PCIC_SHF)
#define ICTA_INTSTATUS_PCIC_SET ICTA_INTSTATUS_PCIC_MSK
/* bit 9: PCIB */
#define ICTA_INTSTATUS_PCIB_SHF 9
#define ICTA_INTSTATUS_PCIB_MSK (MSK(1) << ICTA_INTSTATUS_PCIB_SHF)
#define ICTA_INTSTATUS_PCIB_SET ICTA_INTSTATUS_PCIB_MSK
/* bit 8: PCIA */
#define ICTA_INTSTATUS_PCIA_SHF 8
#define ICTA_INTSTATUS_PCIA_MSK (MSK(1) << ICTA_INTSTATUS_PCIA_SHF)
#define ICTA_INTSTATUS_PCIA_SET ICTA_INTSTATUS_PCIA_MSK
/* bit 7: NMI */
#define ICTA_INTSTATUS_NMI_SHF 7
#define ICTA_INTSTATUS_NMI_MSK (MSK(1) << ICTA_INTSTATUS_NMI_SHF)
#define ICTA_INTSTATUS_NMI_SET ICTA_INTSTATUS_NMI_MSK
/* bit 6: CORELO */
#define ICTA_INTSTATUS_CORELO_SHF 6
#define ICTA_INTSTATUS_CORELO_MSK (MSK(1) << ICTA_INTSTATUS_CORELO_SHF)
#define ICTA_INTSTATUS_CORELO_SET ICTA_INTSTATUS_CORELO_MSK
/* bit 5: COREHI */
#define ICTA_INTSTATUS_COREHI_SHF 5
#define ICTA_INTSTATUS_COREHI_MSK (MSK(1) << ICTA_INTSTATUS_COREHI_SHF)
#define ICTA_INTSTATUS_COREHI_SET ICTA_INTSTATUS_COREHI_MSK
/* bit 4: RTC */
#define ICTA_INTSTATUS_RTC_SHF 4
#define ICTA_INTSTATUS_RTC_MSK (MSK(1) << ICTA_INTSTATUS_RTC_SHF)
#define ICTA_INTSTATUS_RTC_SET ICTA_INTSTATUS_RTC_MSK
/* bit 2: TIM1 */
#define ICTA_INTSTATUS_TIM1_SHF 2
#define ICTA_INTSTATUS_TIM1_MSK (MSK(1) << ICTA_INTSTATUS_TIM1_SHF)
#define ICTA_INTSTATUS_TIM1_SET ICTA_INTSTATUS_TIM1_MSK
/* bit 1: TIM0 */
#define ICTA_INTSTATUS_TIM0_SHF 1
#define ICTA_INTSTATUS_TIM0_MSK (MSK(1) << ICTA_INTSTATUS_TIM0_SHF)
#define ICTA_INTSTATUS_TIM0_SET ICTA_INTSTATUS_TIM0_MSK
/* bit 0: SER */
#define ICTA_INTSTATUS_SER_SHF 0
#define ICTA_INTSTATUS_SER_MSK (MSK(1) << ICTA_INTSTATUS_SER_SHF)
#define ICTA_INTSTATUS_SER_SET ICTA_INTSTATUS_SER_MSK
/************************************************************************
* RTC device: Relative Register Addresses
************************************************************************/
#define RTC_SEC_OFS 0x00 /* seconds register */
#define RTC_SECALARM_OFS 0x01 /* seconds alarm register */
#define RTC_MIN_OFS 0x02 /* minutes register */
#define RTC_MINALARM_OFS 0x03 /* minutes alarm register */
#define RTC_HOUR_OFS 0x04 /* hours register */
#define RTC_HOURALARM_OFS 0x05 /* hours alarm register */
#define RTC_DAYOFWEEK_OFS 0x06 /* day of week register */
#define RTC_DAYOFMONTH_OFS 0x07 /* day of month register */
#define RTC_MONTH_OFS 0x08 /* month register */
#define RTC_YEAR_OFS 0x09 /* year register */
#define RTC_REGA_OFS 0x0A /* register A */
#define RTC_REGB_OFS 0x0B /* register B */
#define RTC_REGC_OFS 0x0C /* register C */
#define RTC_REGD_OFS 0x0D /* register D */
/* RTC Register A bit map definitions */
#define RTC_REGA_UIP_SHF 7
#define RTC_REGA_UIP_MSK (MSK(1) << RTC_REGA_UIP_SHF)
#define RTC_REGA_UIP_BIT RTC_REGA_UIP_MSK
#define RTC_REGA_DCS_SHF 4
#define RTC_REGA_DCS_MSK (MSK(3) << RTC_REGA_DCS_SHF)
#define RTC_REGA_DCS_NORMAL 2 /* Normal operation */
#define RTC_REGA_DCS_RESET 6 /* Divider reset */
#define RTC_REGA_RSB_SHF 0
#define RTC_REGA_RSB_MSK (MSK(4) << RTC_REGA_RSB_SHF)
#define RTC_REGA_RSB_NONE 0 /* No periodic interrupt */
#define RTC_REGA_RSB_3_9 1 /* 3.90625 ms */
#define RTC_REGA_RSB_7_8 2 /* 7.8125 ms */
#define RTC_REGA_RSB_122 3 /* 122.070 us */
#define RTC_REGA_RSB_244 4 /* 244.141 us */
#define RTC_REGA_RSB_488 5 /* 488.281 us */
#define RTC_REGA_RSB_976 6 /* 976.5625 us */
#define RTC_REGA_RSB_1_9 7 /* 1.953125 ms */
#define RTC_REGA_RSB_3_9A 8 /* 3.90625 ms */
#define RTC_REGA_RSB_7_8A 9 /* 7.8125 ms */
#define RTC_REGA_RSB_15 10 /* 15.625 ms */
#define RTC_REGA_RSB_31 11 /* 31.25 ms */
#define RTC_REGA_RSB_62 12 /* 62.5 ms */
#define RTC_REGA_RSB_125 13 /* 125 ms */
#define RTC_REGA_RSB_250 14 /* 250 ms */
#define RTC_REGA_RSB_500 15 /* 500 ms */
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