atlas.h

MIPS架构UCOS-ii移植例程

/**************************************************************************
*                                                                         *
*   PROJECT     : MIPS port for uC/OS-II                                  *
*                                                                         *
*   MODULE      : ATLAS.h                                                 *
*                                                                         *
*   AUTHOR      : Michael Anburaj                                         *
*                 URL  : http://geocities.com/michaelanburaj/             *
*                 EMAIL: [e-mail]                       *
*                                                                         *
*   PROCESSOR   : MIPS 4Kc (32 bit RISC) - ATLAS board                    *
*                                                                         *
*   TOOL-CHAIN  : SDE & Cygnus                                            *
*                                                                         *
*   DESCRIPTION :                                                         *
*   Atlas 4Kc board address-MAP, IO register definition header file.      *
*                                                                         *
**************************************************************************/


#ifndef __ATLAS_H__
#define __ATLAS_H__

#include "sysdefs.h"
#include "mips.h"


/* ********************************************************************* */
/* Module configuration */


/* ********************************************************************* */
/* Interface macro & data definition */

/************************************************************************
 *  Assembly & C address-Maps & Bit fields
*************************************************************************/

/* EEPROM devices,  IIC-slaveadresses */

#define  ATLAS_EEPROM_IICADR_SN       0x54  /* NM24C09, 1024 bytes      */
#define  ATLAS_EEPROM_IICADR_SPD000   0x50  /* PC-SDRAM, 256 bytes      */



/* IIC-bus frequencies for the SAA9730 controller */

#define  ATLAS_IICFREQ_5156HZ         0x05
#define  ATLAS_IICFREQ_10312HZ        0x01
#define  ATLAS_IICFREQ_68750HZ        0x04
#define  ATLAS_IICFREQ_103125HZ       0x06
#define  ATLAS_IICFREQ_275000HZ       0x00
#define  ATLAS_IICFREQ_412500HZ       0x02



/* Physical address MAP (512 MByte) */

#define  ATLAS_SYSTEMRAM_BASE         0x00000000 /* System RAM:     */
#define  ATLAS_SYSTEMRAM_SIZE         0x10000000 /*   256 MByte     */

#define  ATLAS_PCIMEM1_BASE           0x10000000 /* PCI 1 memory:   */
#define  ATLAS_PCIMEM1_SIZE           0x0be00000 /*  128 + 60 MByte */

#define  ATLAS_PCIMEM2_BASE           0x18000000 /* PCI 2 memory    */
#define  ATLAS_PCIMEM2_SIZE           0x00200000 /*     2 MByte     */

#define  ATLAS_CORECTRL_BASE          0x1BE00000 /* Core control:   */
#define  ATLAS_CORECTRL_SIZE          0x00200000 /*     2 MByte     */

#define  ATLAS_SYSTEMFLASH_BASE       0x1C000000 /* System Flash:   */
#define  ATLAS_SYSTEMFLASH_SIZE       0x02000000 /*    32 MByte     */

#define  ATLAS_SYSTEMFLASH_SECTORSIZE 0x00020000 /* Sect. = 128 KB  */
#define  ATLAS_SYSTEMFLASH_BANKCOUNT           2 /*                 */
#define  ATLAS_SYSTEMFLASH_BLOCKCOUNT         64 /*                 */

#define  ATLAS_MONITORFLASH_BASE      0x1E000000 /* Monitor Flash:  */
#define  ATLAS_MONITORFLASH_SIZE      0x003E0000 /*     4 MByte     */
#define  ATLAS_MONITORFLASH_SECTORSIZE 0x00010000 /* Sect. = 64 KB  */

#define  ATLAS_RESERVED_BASE          0x1E400000 /* Reserved:       */
#define  ATLAS_RESERVED_SIZE          0x00C00000 /*    12 MByte     */

#define  ATLAS_FPGA_BASE              0x1F000000 /* FPGA:           */
#define  ATLAS_FPGA_SIZE              0x00C00000 /*    12 MByte     */

#define  ATLAS_BOOTROM_BASE           0x1FC00000 /* Boot ROM:       */
#define  ATLAS_BOOTROM_SIZE           0x00400000 /*     4 MByte     */



/* Use of PCI ranges (Memory vs I/O) */

#define  ATLAS_PCI_MEM_BASE           ATLAS_PCIMEM1_BASE
#define  ATLAS_PCI_MEM_SIZE           ATLAS_PCIMEM1_SIZE

#define  ATLAS_PCI_IO_BASE            ATLAS_PCIMEM2_BASE
#define  ATLAS_PCI_IO_SIZE            ATLAS_PCIMEM2_SIZE



/* FILEFLASH: upper 128 KByte (2x64 KByte sectors) of MONITORFLASH */

#define  ATLAS_FILEFLASH_BASE         0x1E3E0000 /* File Flash:     */
#define  ATLAS_FILEFLASH_SIZE         0x00020000 /*   128 KByte     */

#define  ATLAS_FILEFLASH_SECTORSIZE   0x00010000 /* Sect. = 64 KB   */



/* Devices, base adresses */

#define  ATLAS_ICTA_BASE              0x1F000000 /* FPGA, Int. ctrl,
                                                    ref. icta defs      */
#define  ATLAS_TMRA_BASE              0x1F000300 /* FPGA, Timer device,
                                                    ref. 'tmra.h'       */
#define  ATLAS_TI16C550_BASE          0x1F000900 /* TI16C550 UART,
                                                    upper connector     */


                                                    
/* FPGA, register address map */
/* REVISION: MUST BE FIXED TO  0x1FC00010 on any baseboard */

/******** reg: REVISION ********/
#define ATLAS_REVISION                0x1FC00010 /* REVISION              */

/* field: FPGRV */
#define ATLAS_REVISION_FPGRV_SHF      16
#define ATLAS_REVISION_FPGRV_MSK      (MSK(8) << ATLAS_REVISION_FPGRV_SHF)

/* field: CORID */
#define ATLAS_REVISION_CORID_SHF      10
#define ATLAS_REVISION_CORID_MSK      (MSK(6) << ATLAS_REVISION_CORID_SHF)

/* field: CORRV */
#define ATLAS_REVISION_CORRV_SHF      8
#define ATLAS_REVISION_CORRV_MSK      (MSK(2) << ATLAS_REVISION_CORRV_SHF)

/* field: PROID */
#define ATLAS_REVISION_PROID_SHF      4
#define ATLAS_REVISION_PROID_MSK      (MSK(4) << ATLAS_REVISION_PROID_SHF)

/* field: PRORV */
#define ATLAS_REVISION_PRORV_SHF      0
#define ATLAS_REVISION_PRORV_MSK      (MSK(4) << ATLAS_REVISION_PRORV_SHF)



/******** reg: HWINTACK ********/
#define ATLAS_HWINTACK                0x1F000100 /* HWINTACK              */

/* bit 1: ACKDEG */
#define ATLAS_HWINTACK_ACKDEG_SHF     1
#define ATLAS_HWINTACK_ACKDEG_MSK     (MSK(1) << ATLAS_HWINTACK_ACKDEG_SHF)
#define ATLAS_HWINTACK_ACKDEG_SET     ATLAS_HWINTACK_ACKDEG_MSK



/******** reg: NMISTATUS ********/
#define ATLAS_NMISTATUS               0x1F000024 /* NMISTATUS    */

/* bit 0: NMISTATUS */
#define ATLAS_NMISTATUS_ONNMI_SHF     0
#define ATLAS_NMISTATUS_ONNMI_MSK     (MSK(1) << ATLAS_NMISTATUS_ONNMI_SHF)
#define ATLAS_NMISTATUS_ONNMI_BIT     ATLAS_NMISTATUS_ONNMI_MSK    



/******** reg: NMIACK ********/
#define ATLAS_NMIACK                  0x1F000104 /* NMIACK        */

/* bit 0: NMI */
#define ATLAS_NMIACK_ONNMI_SHF        0
#define ATLAS_NMIACK_ONNMI_MSK        (MSK(1) << ATLAS_NMIACK_ONNMI_SHF)
#define ATLAS_NMIACK_ONNMI_BIT        ATLAS_NMIACK_ONNMI_MSK



/******** reg: SWVALUE ********/
#define ATLAS_SWVALUE                 0x1F000200 /* SWVALUE               */

/* bit 11: S14 */
#define ATLAS_SWVALUE_S14_SHF         11
#define ATLAS_SWVALUE_S14_MSK         (MSK(1) << ATLAS_SWVALUE_S14_SHF)
#define ATLAS_SWVALUE_S14_SET         ATLAS_SWVALUE_S14_MSK

/* bit 10: S13 */
#define ATLAS_SWVALUE_S13_SHF         10
#define ATLAS_SWVALUE_S13_MSK         (MSK(1) << ATLAS_SWVALUE_S13_SHF)
#define ATLAS_SWVALUE_S13_SET         ATLAS_SWVALUE_S13_MSK

/* bit 9: S12 */
#define ATLAS_SWVALUE_S12_SHF         9
#define ATLAS_SWVALUE_S12_MSK         (MSK(1) << ATLAS_SWVALUE_S12_SHF)
#define ATLAS_SWVALUE_S12_SET         ATLAS_SWVALUE_S12_MSK

/* bit 8: S11 */
#define ATLAS_SWVALUE_S11_SHF         8
#define ATLAS_SWVALUE_S11_MSK         (MSK(1) << ATLAS_SWVALUE_S11_SHF)
#define ATLAS_SWVALUE_S11_SET         ATLAS_SWVALUE_S11_MSK

/* bits 7:0: S2 */
#define ATLAS_SWVALUE_S2_SHF          0
#define ATLAS_SWVALUE_S2_MSK          (MSK(8) << ATLAS_SWVALUE_S2_SHF)



/******** reg: STATUS ********/
#define ATLAS_STATUS                  0x1F000208 /* STATUS                */

/* bit 4 : MFWR */
#define ATLAS_STATUS_MFWR_SHF         4
#define ATLAS_STATUS_MFWR_MSK         (MSK(1) << ATLAS_STATUS_MFWR_SHF)
#define ATLAS_STATUS_MFWR_SET         ATLAS_STATUS_MFWR_MSK

/* bit 3 : S54 */
#define ATLAS_STATUS_S54_SHF          3
#define ATLAS_STATUS_S54_MSK          (MSK(1) << ATLAS_STATUS_S54_SHF)
#define ATLAS_STATUS_S54_SET          ATLAS_STATUS_S54_MSK

/* bit 2 : S53 */
#define ATLAS_STATUS_S53_SHF          2
#define ATLAS_STATUS_S53_MSK          (MSK(1) << ATLAS_STATUS_S53_SHF)
#define ATLAS_STATUS_S53_SET          ATLAS_STATUS_S53_MSK

/* bit 1: BIGEND */
#define ATLAS_STATUS_BIGEND_SHF       1
#define ATLAS_STATUS_BIGEND_MSK       (MSK(1) << ATLAS_STATUS_BIGEND_SHF)
#define ATLAS_STATUS_BIGEND_SET       ATLAS_STATUS_BIGEND_MSK

/* bit 0: PCISYS */
#define ATLAS_STATUS_PCISYS_SHF       0
#define ATLAS_STATUS_PCISYS_MSK       (MSK(1) << ATLAS_STATUS_PCISYS_SHF)
#define ATLAS_STATUS_PCISYS_SET       ATLAS_STATUS_PCISYS_MSK



/******** reg: JMPRS ********/
#define ATLAS_JMPRS                   0x1F000210 /* JMPRS                 */

/* bit 1: EELOCK */
#define ATLAS_JMPRS_EELOCK_SHF        1
#define ATLAS_JMPRS_EELOCK_MSK        (MSK(1) << ATLAS_JMPRS_EELOCK_SHF)
#define ATLAS_JMPRS_EELOCK_SET        ATLAS_JMPRS_EELOCK_MSK

/* bit 0: PCI33M */
#define ATLAS_JMPRS_PCI33M_SHF        0
#define ATLAS_JMPRS_PCI33M_MSK        (MSK(1) << ATLAS_JMPRS_PCI33M_SHF)
#define ATLAS_JMPRS_PCI33M_SET        ATLAS_JMPRS_PCI33M_MSK



/******** reg: LEDGREEN ********/
#define ATLAS_LEDGREEN                0x1F000400 /* LEDGREEN              */

/* bits 0: ON */
#define ATLAS_LEDGREEN_ON_SHF         0
#define ATLAS_LEDGREEN_ON_MSK         (MSK(1) << ATLAS_LEDGREEN_ON_SHF)
#define ATLAS_LEDGREEN_ON_SET         ATLAS_LEDGREEN_ON_MSK



/******** reg: LEDBAR ********/
#define ATLAS_LEDBAR                  0x1F000408 /* LEDBAR                */



/******** reg: ASCII LED ********/
#define ATLAS_ASCIIWORD               0x1F000410 /* ASCIIWORD             */
#define ATLAS_ASCIIPOS0               0x1F000418 /* ASCIIPOS0             */
#define ATLAS_ASCIIPOS1               0x1F000420 /* ASCIIPOS1             */
#define ATLAS_ASCIIPOS2               0x1F000428 /* ASCIIPOS2             */
#define ATLAS_ASCIIPOS3               0x1F000430 /* ASCIIPOS3             */
#define ATLAS_ASCIIPOS4               0x1F000438 /* ASCIIPOS4             */
#define ATLAS_ASCIIPOS5               0x1F000440 /* ASCIIPOS5             */
#define ATLAS_ASCIIPOS6               0x1F000448 /* ASCIIPOS6             */
#define ATLAS_ASCIIPOS7               0x1F000450 /* ASCIIPOS7             */



/******** reg: SOFTRES ********/
#define ATLAS_SOFTRES                 0x1F000500 /* SOFTRES               */

/* bits 7:0: RESET */
#define ATLAS_SOFTRES_RESET_SHF       0
#define ATLAS_SOFTRES_RESET_MSK       (MSK(8) << ATLAS_SOFTRES_RESET_SHF)
#define ATLAS_SOFTRES_RESET_GORESET   0x42     /* magic value to reset    */    



/******** reg: BRKRES ********/
#define ATLAS_BRKRES                  0x1F000508 /* BRKRES                */

/* bits 7:0: WIDTH */
#define ATLAS_BRKRES_WIDTH_SHF        0
#define ATLAS_BRKRES_WIDTH_MSK        (MSK(8) << ATLAS_BRKRES_WIDTH_SHF)



/******** reg: PSUSTBY ********/
#define ATLAS_PSUSTBY                 0x1F000600 /* PSUSTBY               */

/* bits 7:0: STBY */
#define ATLAS_PSUSTBY_STBY_SHF        0
#define ATLAS_PSUSTBY_STBY_MSK        (MSK(8) << ATLAS_PSUSTBY_STBY_SHF)
#define ATLAS_PSUSTBY_STBY_GOSTBY     0x4D     /* magic value to go stby  */    



/******** reg: SFWCTRL ********/
#define ATLAS_SFWCTRL                 0x1F000700 /* SFWCTRL               */

/* bits 7:0: WRENA */
#define ATLAS_SFWCTRL_WRENA_SHF       0
#define ATLAS_SFWCTRL_WRENA_MSK       (MSK(8) << ATLAS_SFWCTRL_WRENA_SHF)
#define ATLAS_SFWCTRL_WRENA_ENSFWRITE 0xC7   /* magic value to enable 
                                                write protect           */