📄 stm32f10x_gpio.lst
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###############################################################################
# #
# IAR ANSI C/C++ Compiler V6.10.2.52244/W32 for ARM 07/Aug/2011 12:10:20 #
# Copyright 1999-2010 IAR Systems AB. #
# #
# Cpu mode = thumb #
# Endian = little #
# Source file = F:\stm32\我的程序\Micrium\Software\EWARM\BSP\ST\STM32F10 #
# x_StdPeriph_Driver\src\stm32f10x_gpio.c #
# Command line = F:\stm32\我的程序\Micrium\Software\EWARM\BSP\ST\STM32F10 #
# x_StdPeriph_Driver\src\stm32f10x_gpio.c -D #
# USE_STDPERIPH_DRIVER -D STM32F10X_CL -lCN #
# F:\stm32\我的程序\Micrium\Software\EWARM\OS-II\Flash\Lis #
# t\ -o F:\stm32\我的程序\Micrium\Software\EWARM\OS-II\Fla #
# sh\Obj\ --no_cse --no_unroll --no_inline #
# --no_code_motion --no_tbaa --no_clustering #
# --no_scheduling --debug --endian=little --cpu=Cortex-M3 #
# -e --fpu=None --dlib_config #
# D:\arm\INC\c\DLib_Config_Normal.h -I #
# F:\stm32\我的程序\Micrium\Software\EWARM\OS-II\APP\ -I #
# F:\stm32\我的程序\Micrium\Software\EWARM\OS-II\..\BSP\ #
# -I F:\stm32\我的程序\Micrium\Software\EWARM\OS-II\..\BSP #
# \ST\CMSIS\CM3\CoreSupport\ -I #
# F:\stm32\我的程序\Micrium\Software\EWARM\OS-II\..\BSP\ST #
# \CMSIS\CM3\DeviceSupport\ST\STM32F10x\ -I #
# F:\stm32\我的程序\Micrium\Software\EWARM\OS-II\..\BSP\ST #
# \STM32F10x_StdPeriph_Driver\inc\ -I #
# F:\stm32\我的程序\Micrium\Software\EWARM\OS-II\..\BSP\uC #
# OS-II\ -I F:\stm32\我的程序\Micrium\Software\EWARM\OS-II #
# \..\..\uCOS-II\Ports\ARM-Cortex-M3\Generic\IAR\ -I #
# F:\stm32\我的程序\Micrium\Software\EWARM\OS-II\..\..\uCO #
# S-II\Source\ -I F:\stm32\我的程序\Micrium\Software\EWARM #
# \OS-II\..\..\uC-LIB\ -I F:\stm32\我的程序\Micrium\Softwa #
# re\EWARM\OS-II\..\..\uC-LIB\Ports\ARM-Cortex-M3\IAR\ -I #
# F:\stm32\我的程序\Micrium\Software\EWARM\OS-II\..\..\uC- #
# CPU\ -I F:\stm32\我的程序\Micrium\Software\EWARM\OS-II\. #
# .\..\uC-CPU\ARM-Cortex-M3\IAR\ -On --use_c++_inline #
# List file = F:\stm32\我的程序\Micrium\Software\EWARM\OS-II\Flash\Lis #
# t\stm32f10x_gpio.lst #
# Object file = F:\stm32\我的程序\Micrium\Software\EWARM\OS-II\Flash\Obj #
# \stm32f10x_gpio.o #
# #
# #
###############################################################################
F:\stm32\我的程序\Micrium\Software\EWARM\BSP\ST\STM32F10x_StdPeriph_Driver\src\stm32f10x_gpio.c
1 /**
2 ******************************************************************************
3 * @file stm32f10x_gpio.c
4 * @author MCD Application Team
5 * @version V3.4.0
6 * @date 10/15/2010
7 * @brief This file provides all the GPIO firmware functions.
8 ******************************************************************************
9 * @copy
10 *
11 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
12 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
13 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
14 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
15 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
16 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
17 *
18 * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
19 */
20
21 /* Includes ------------------------------------------------------------------*/
22 #include "stm32f10x_gpio.h"
23 #include "stm32f10x_rcc.h"
24
25 /** @addtogroup STM32F10x_StdPeriph_Driver
26 * @{
27 */
28
29 /** @defgroup GPIO
30 * @brief GPIO driver modules
31 * @{
32 */
33
34 /** @defgroup GPIO_Private_TypesDefinitions
35 * @{
36 */
37
38 /**
39 * @}
40 */
41
42 /** @defgroup GPIO_Private_Defines
43 * @{
44 */
45
46 /* ------------ RCC registers bit address in the alias region ----------------*/
47 #define AFIO_OFFSET (AFIO_BASE - PERIPH_BASE)
48
49 /* --- EVENTCR Register -----*/
50
51 /* Alias word address of EVOE bit */
52 #define EVCR_OFFSET (AFIO_OFFSET + 0x00)
53 #define EVOE_BitNumber ((uint8_t)0x07)
54 #define EVCR_EVOE_BB (PERIPH_BB_BASE + (EVCR_OFFSET * 32) + (EVOE_BitNumber * 4))
55
56
57 /* --- MAPR Register ---*/
58 /* Alias word address of MII_RMII_SEL bit */
59 #define MAPR_OFFSET (AFIO_OFFSET + 0x04)
60 #define MII_RMII_SEL_BitNumber ((u8)0x17)
61 #define MAPR_MII_RMII_SEL_BB (PERIPH_BB_BASE + (MAPR_OFFSET * 32) + (MII_RMII_SEL_BitNumber * 4))
62
63
64 #define EVCR_PORTPINCONFIG_MASK ((uint16_t)0xFF80)
65 #define LSB_MASK ((uint16_t)0xFFFF)
66 #define DBGAFR_POSITION_MASK ((uint32_t)0x000F0000)
67 #define DBGAFR_SWJCFG_MASK ((uint32_t)0xF0FFFFFF)
68 #define DBGAFR_LOCATION_MASK ((uint32_t)0x00200000)
69 #define DBGAFR_NUMBITS_MASK ((uint32_t)0x00100000)
70 /**
71 * @}
72 */
73
74 /** @defgroup GPIO_Private_Macros
75 * @{
76 */
77
78 /**
79 * @}
80 */
81
82 /** @defgroup GPIO_Private_Variables
83 * @{
84 */
85
86 /**
87 * @}
88 */
89
90 /** @defgroup GPIO_Private_FunctionPrototypes
91 * @{
92 */
93
94 /**
95 * @}
96 */
97
98 /** @defgroup GPIO_Private_Functions
99 * @{
100 */
101
102 /**
103 * @brief Deinitializes the GPIOx peripheral registers to their default reset values.
104 * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
105 * @retval None
106 */
\ In section .text, align 2, keep-with-next
107 void GPIO_DeInit(GPIO_TypeDef* GPIOx)
108 {
\ GPIO_DeInit:
\ 00000000 10B5 PUSH {R4,LR}
\ 00000002 0400 MOVS R4,R0
109 /* Check the parameters */
110 assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
111
112 if (GPIOx == GPIOA)
\ 00000004 ........ LDR.W R0,??DataTable5 ;; 0x40010800
\ 00000008 8442 CMP R4,R0
\ 0000000A 08D1 BNE.N ??GPIO_DeInit_0
113 {
114 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, ENABLE);
\ 0000000C 0121 MOVS R1,#+1
\ 0000000E 0420 MOVS R0,#+4
\ 00000010 ........ BL RCC_APB2PeriphResetCmd
115 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, DISABLE);
\ 00000014 0021 MOVS R1,#+0
\ 00000016 0420 MOVS R0,#+4
\ 00000018 ........ BL RCC_APB2PeriphResetCmd
\ 0000001C 49E0 B.N ??GPIO_DeInit_1
116 }
117 else if (GPIOx == GPIOB)
\ ??GPIO_DeInit_0:
\ 0000001E ........ LDR.W R0,??DataTable5_1 ;; 0x40010c00
\ 00000022 8442 CMP R4,R0
\ 00000024 08D1 BNE.N ??GPIO_DeInit_2
118 {
119 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, ENABLE);
\ 00000026 0121 MOVS R1,#+1
\ 00000028 0820 MOVS R0,#+8
\ 0000002A ........ BL RCC_APB2PeriphResetCmd
120 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, DISABLE);
\ 0000002E 0021 MOVS R1,#+0
\ 00000030 0820 MOVS R0,#+8
\ 00000032 ........ BL RCC_APB2PeriphResetCmd
\ 00000036 3CE0 B.N ??GPIO_DeInit_1
121 }
122 else if (GPIOx == GPIOC)
\ ??GPIO_DeInit_2:
\ 00000038 .... LDR.N R0,??DataTable5_2 ;; 0x40011000
\ 0000003A 8442 CMP R4,R0
\ 0000003C 08D1 BNE.N ??GPIO_DeInit_3
123 {
124 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, ENABLE);
\ 0000003E 0121 MOVS R1,#+1
\ 00000040 1020 MOVS R0,#+16
\ 00000042 ........ BL RCC_APB2PeriphResetCmd
125 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, DISABLE);
\ 00000046 0021 MOVS R1,#+0
\ 00000048 1020 MOVS R0,#+16
\ 0000004A ........ BL RCC_APB2PeriphResetCmd
\ 0000004E 30E0 B.N ??GPIO_DeInit_1
126 }
127 else if (GPIOx == GPIOD)
\ ??GPIO_DeInit_3:
\ 00000050 .... LDR.N R0,??DataTable5_3 ;; 0x40011400
\ 00000052 8442 CMP R4,R0
\ 00000054 08D1 BNE.N ??GPIO_DeInit_4
128 {
129 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, ENABLE);
\ 00000056 0121 MOVS R1,#+1
\ 00000058 2020 MOVS R0,#+32
\ 0000005A ........ BL RCC_APB2PeriphResetCmd
130 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, DISABLE);
\ 0000005E 0021 MOVS R1,#+0
\ 00000060 2020 MOVS R0,#+32
\ 00000062 ........ BL RCC_APB2PeriphResetCmd
\ 00000066 24E0 B.N ??GPIO_DeInit_1
131 }
132 else if (GPIOx == GPIOE)
\ ??GPIO_DeInit_4:
\ 00000068 .... LDR.N R0,??DataTable5_4 ;; 0x40011800
\ 0000006A 8442 CMP R4,R0
\ 0000006C 08D1 BNE.N ??GPIO_DeInit_5
133 {
134 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, ENABLE);
\ 0000006E 0121 MOVS R1,#+1
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