📄 stm32f10x_adc.lst
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622 tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel);
\ 0000004C DBB2 UXTB R3,R3 ;; ZeroExt R3,R3,#+24,#+24
\ 0000004E 0326 MOVS R6,#+3
\ 00000050 06FB01F6 MUL R6,R6,R1
\ 00000054 13FA06F6 LSLS R6,R3,R6
\ 00000058 3400 MOVS R4,R6
623 /* Set the new channel sample time */
624 tmpreg1 |= tmpreg2;
\ 0000005A 2543 ORRS R5,R4,R5
625 /* Store the new register value */
626 ADCx->SMPR2 = tmpreg1;
\ 0000005C 0561 STR R5,[R0, #+16]
627 }
628 /* For Rank 1 to 6 */
629 if (Rank < 7)
\ ??ADC_RegularChannelConfig_1:
\ 0000005E D2B2 UXTB R2,R2 ;; ZeroExt R2,R2,#+24,#+24
\ 00000060 072A CMP R2,#+7
\ 00000062 14D2 BCS.N ??ADC_RegularChannelConfig_2
630 {
631 /* Get the old register value */
632 tmpreg1 = ADCx->SQR3;
\ 00000064 466B LDR R6,[R0, #+52]
\ 00000066 3500 MOVS R5,R6
633 /* Calculate the mask to clear */
634 tmpreg2 = SQR3_SQ_Set << (5 * (Rank - 1));
\ 00000068 1F26 MOVS R6,#+31
\ 0000006A 571E SUBS R7,R2,#+1
\ 0000006C 5FF0050C MOVS R12,#+5
\ 00000070 0CFB07F7 MUL R7,R12,R7
\ 00000074 BE40 LSLS R6,R6,R7
\ 00000076 3400 MOVS R4,R6
635 /* Clear the old SQx bits for the selected rank */
636 tmpreg1 &= ~tmpreg2;
\ 00000078 A543 BICS R5,R5,R4
637 /* Calculate the mask to set */
638 tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 1));
\ 0000007A C9B2 UXTB R1,R1 ;; ZeroExt R1,R1,#+24,#+24
\ 0000007C 561E SUBS R6,R2,#+1
\ 0000007E 0527 MOVS R7,#+5
\ 00000080 7E43 MULS R6,R7,R6
\ 00000082 11FA06F6 LSLS R6,R1,R6
\ 00000086 3400 MOVS R4,R6
639 /* Set the SQx bits for the selected rank */
640 tmpreg1 |= tmpreg2;
\ 00000088 2543 ORRS R5,R4,R5
641 /* Store the new register value */
642 ADCx->SQR3 = tmpreg1;
\ 0000008A 4563 STR R5,[R0, #+52]
\ 0000008C 2DE0 B.N ??ADC_RegularChannelConfig_3
643 }
644 /* For Rank 7 to 12 */
645 else if (Rank < 13)
\ ??ADC_RegularChannelConfig_2:
\ 0000008E D2B2 UXTB R2,R2 ;; ZeroExt R2,R2,#+24,#+24
\ 00000090 0D2A CMP R2,#+13
\ 00000092 14D2 BCS.N ??ADC_RegularChannelConfig_4
646 {
647 /* Get the old register value */
648 tmpreg1 = ADCx->SQR2;
\ 00000094 066B LDR R6,[R0, #+48]
\ 00000096 3500 MOVS R5,R6
649 /* Calculate the mask to clear */
650 tmpreg2 = SQR2_SQ_Set << (5 * (Rank - 7));
\ 00000098 1F26 MOVS R6,#+31
\ 0000009A D71F SUBS R7,R2,#+7
\ 0000009C 5FF0050C MOVS R12,#+5
\ 000000A0 0CFB07F7 MUL R7,R12,R7
\ 000000A4 BE40 LSLS R6,R6,R7
\ 000000A6 3400 MOVS R4,R6
651 /* Clear the old SQx bits for the selected rank */
652 tmpreg1 &= ~tmpreg2;
\ 000000A8 A543 BICS R5,R5,R4
653 /* Calculate the mask to set */
654 tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 7));
\ 000000AA C9B2 UXTB R1,R1 ;; ZeroExt R1,R1,#+24,#+24
\ 000000AC D61F SUBS R6,R2,#+7
\ 000000AE 0527 MOVS R7,#+5
\ 000000B0 7E43 MULS R6,R7,R6
\ 000000B2 11FA06F6 LSLS R6,R1,R6
\ 000000B6 3400 MOVS R4,R6
655 /* Set the SQx bits for the selected rank */
656 tmpreg1 |= tmpreg2;
\ 000000B8 2543 ORRS R5,R4,R5
657 /* Store the new register value */
658 ADCx->SQR2 = tmpreg1;
\ 000000BA 0563 STR R5,[R0, #+48]
\ 000000BC 15E0 B.N ??ADC_RegularChannelConfig_3
659 }
660 /* For Rank 13 to 16 */
661 else
662 {
663 /* Get the old register value */
664 tmpreg1 = ADCx->SQR1;
\ ??ADC_RegularChannelConfig_4:
\ 000000BE C66A LDR R6,[R0, #+44]
\ 000000C0 3500 MOVS R5,R6
665 /* Calculate the mask to clear */
666 tmpreg2 = SQR1_SQ_Set << (5 * (Rank - 13));
\ 000000C2 1F26 MOVS R6,#+31
\ 000000C4 B2F10D07 SUBS R7,R2,#+13
\ 000000C8 5FF0050C MOVS R12,#+5
\ 000000CC 0CFB07F7 MUL R7,R12,R7
\ 000000D0 BE40 LSLS R6,R6,R7
\ 000000D2 3400 MOVS R4,R6
667 /* Clear the old SQx bits for the selected rank */
668 tmpreg1 &= ~tmpreg2;
\ 000000D4 A543 BICS R5,R5,R4
669 /* Calculate the mask to set */
670 tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 13));
\ 000000D6 C9B2 UXTB R1,R1 ;; ZeroExt R1,R1,#+24,#+24
\ 000000D8 B2F10D06 SUBS R6,R2,#+13
\ 000000DC 0527 MOVS R7,#+5
\ 000000DE 7E43 MULS R6,R7,R6
\ 000000E0 11FA06F6 LSLS R6,R1,R6
\ 000000E4 3400 MOVS R4,R6
671 /* Set the SQx bits for the selected rank */
672 tmpreg1 |= tmpreg2;
\ 000000E6 2543 ORRS R5,R4,R5
673 /* Store the new register value */
674 ADCx->SQR1 = tmpreg1;
\ 000000E8 C562 STR R5,[R0, #+44]
675 }
676 }
\ ??ADC_RegularChannelConfig_3:
\ 000000EA F0BC POP {R4-R7}
\ 000000EC 7047 BX LR ;; return
677
678 /**
679 * @brief Enables or disables the ADCx conversion through external trigger.
680 * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
681 * @param NewState: new state of the selected ADC external trigger start of conversion.
682 * This parameter can be: ENABLE or DISABLE.
683 * @retval None
684 */
\ In section .text, align 2, keep-with-next
685 void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
686 {
687 /* Check the parameters */
688 assert_param(IS_ADC_ALL_PERIPH(ADCx));
689 assert_param(IS_FUNCTIONAL_STATE(NewState));
690 if (NewState != DISABLE)
\ ADC_ExternalTrigConvCmd:
\ 00000000 C9B2 UXTB R1,R1 ;; ZeroExt R1,R1,#+24,#+24
\ 00000002 0029 CMP R1,#+0
\ 00000004 04D0 BEQ.N ??ADC_ExternalTrigConvCmd_0
691 {
692 /* Enable the selected ADC conversion on external event */
693 ADCx->CR2 |= CR2_EXTTRIG_Set;
\ 00000006 8268 LDR R2,[R0, #+8]
\ 00000008 52F48012 ORRS R2,R2,#0x100000
\ 0000000C 8260 STR R2,[R0, #+8]
\ 0000000E 03E0 B.N ??ADC_ExternalTrigConvCmd_1
694 }
695 else
696 {
697 /* Disable the selected ADC conversion on external event */
698 ADCx->CR2 &= CR2_EXTTRIG_Reset;
\ ??ADC_ExternalTrigConvCmd_0:
\ 00000010 8268 LDR R2,[R0, #+8]
\ 00000012 32F48012 BICS R2,R2,#0x100000
\ 00000016 8260 STR R2,[R0, #+8]
699 }
700 }
\ ??ADC_ExternalTrigConvCmd_1:
\ 00000018 7047 BX LR ;; return
701
702 /**
703 * @brief Returns the last ADCx conversion result data for regular channel.
704 * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
705 * @retval The Data conversion value.
706 */
\ In section .text, align 2, keep-with-next
707 uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx)
708 {
709 /* Check the parameters */
710 assert_param(IS_ADC_ALL_PERIPH(ADCx));
711 /* Return the selected ADC conversion value */
712 return (uint16_t) ADCx->DR;
\ ADC_GetConversionValue:
\ 00000000 C06C LDR R0,[R0, #+76]
\ 00000002 80B2 UXTH R0,R0 ;; ZeroExt R0,R0,#+16,#+16
\ 00000004 7047 BX LR ;; return
713 }
714
715 /**
716 * @brief Returns the last ADC1 and ADC2 conversion result data in dual mode.
717 * @retval The Data conversion value.
718 */
\ In section .text, align 2, keep-with-next
719 uint32_t ADC_GetDualModeConversionValue(void)
720 {
721 /* Return the dual mode conversion value */
722 return (*(__IO uint32_t *) DR_ADDRESS);
\ ADC_GetDualModeConversionValue:
\ 00000000 .... LDR.N R0,??DataTable4_5 ;; 0x4001244c
\ 00000002 0068 LDR R0,[R0, #+0]
\ 00000004 7047 BX LR ;; return
723 }
724
725 /**
726 * @brief Enables or disables the selected ADC automatic injected group
727 * conversion after regular one.
728 * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
729 * @param NewState: new state of the selected ADC auto injected conversion
730 * This parameter can be: ENABLE or DISABLE.
731 * @retval None
732 */
\ In section .text, align 2, keep-with-next
733 void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
734 {
735 /* Check the parameters */
736 assert_param(IS_ADC_ALL_PERIPH(ADCx));
737 assert_param(IS_FUNCTIONAL_STATE(NewState));
738 if (NewState != DISABLE)
\ ADC_AutoInjectedConvCmd:
\ 00000000 C9B2 UXTB R1,R1 ;; ZeroExt R1,R1,#+24,#+24
\ 00000002 0029 CMP R1,#+0
\ 00000004 04D0 BEQ.N ??ADC_AutoInjectedConvCmd_0
739 {
740 /* Enable the selected ADC automatic injected group conversion */
741 ADCx->CR1 |= CR1_JAUTO_Set;
\ 00000006 4268 LDR R2,[R0, #+4]
\ 00000008 52F48062 ORRS R2,R2,#0x400
\ 0000000C 4260 STR R2,[R0, #+4]
\ 0000000E 03E0 B.N ??ADC_AutoInjectedConvCmd_1
742 }
743 else
744 {
745 /* Disable the selected ADC automatic injected group conversion */
746 ADCx->CR1 &= CR1_JAUTO_Reset;
\ ??ADC_AutoInjectedConvCmd_0:
\ 00000010 4268 LDR R2,[R0, #+4]
\ 00000012 32F48062 BICS R2,R2,#0x400
\ 00000016 4260 STR R2,[R0, #+4]
747 }
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