📄 stm32f10x_adc.lst
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\ ??ADC_SoftwareStartConvCmd_0:
\ 00000010 8268 LDR R2,[R0, #+8]
\ 00000012 32F4A002 BICS R2,R2,#0x500000
\ 00000016 8260 STR R2,[R0, #+8]
472 }
473 }
\ ??ADC_SoftwareStartConvCmd_1:
\ 00000018 7047 BX LR ;; return
474
475 /**
476 * @brief Gets the selected ADC Software start conversion Status.
477 * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
478 * @retval The new state of ADC software start conversion (SET or RESET).
479 */
\ In section .text, align 2, keep-with-next
480 FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx)
481 {
\ ADC_GetSoftwareStartConvStatus:
\ 00000000 0100 MOVS R1,R0
482 FlagStatus bitstatus = RESET;
\ 00000002 0020 MOVS R0,#+0
483 /* Check the parameters */
484 assert_param(IS_ADC_ALL_PERIPH(ADCx));
485 /* Check the status of SWSTART bit */
486 if ((ADCx->CR2 & CR2_SWSTART_Set) != (uint32_t)RESET)
\ 00000004 8A68 LDR R2,[R1, #+8]
\ 00000006 5202 LSLS R2,R2,#+9
\ 00000008 02D5 BPL.N ??ADC_GetSoftwareStartConvStatus_0
487 {
488 /* SWSTART bit is set */
489 bitstatus = SET;
\ 0000000A 0122 MOVS R2,#+1
\ 0000000C 1000 MOVS R0,R2
\ 0000000E 01E0 B.N ??ADC_GetSoftwareStartConvStatus_1
490 }
491 else
492 {
493 /* SWSTART bit is reset */
494 bitstatus = RESET;
\ ??ADC_GetSoftwareStartConvStatus_0:
\ 00000010 0022 MOVS R2,#+0
\ 00000012 1000 MOVS R0,R2
495 }
496 /* Return the SWSTART bit status */
497 return bitstatus;
\ ??ADC_GetSoftwareStartConvStatus_1:
\ 00000014 C0B2 UXTB R0,R0 ;; ZeroExt R0,R0,#+24,#+24
\ 00000016 7047 BX LR ;; return
498 }
499
500 /**
501 * @brief Configures the discontinuous mode for the selected ADC regular
502 * group channel.
503 * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
504 * @param Number: specifies the discontinuous mode regular channel
505 * count value. This number must be between 1 and 8.
506 * @retval None
507 */
\ In section .text, align 2, keep-with-next
508 void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number)
509 {
\ ADC_DiscModeChannelCountConfig:
\ 00000000 10B4 PUSH {R4}
510 uint32_t tmpreg1 = 0;
\ 00000002 0022 MOVS R2,#+0
511 uint32_t tmpreg2 = 0;
\ 00000004 0023 MOVS R3,#+0
512 /* Check the parameters */
513 assert_param(IS_ADC_ALL_PERIPH(ADCx));
514 assert_param(IS_ADC_REGULAR_DISC_NUMBER(Number));
515 /* Get the old register value */
516 tmpreg1 = ADCx->CR1;
\ 00000006 4468 LDR R4,[R0, #+4]
\ 00000008 2200 MOVS R2,R4
517 /* Clear the old discontinuous mode channel count */
518 tmpreg1 &= CR1_DISCNUM_Reset;
\ 0000000A 32F46042 BICS R2,R2,#0xE000
519 /* Set the discontinuous mode channel count */
520 tmpreg2 = Number - 1;
\ 0000000E C9B2 UXTB R1,R1 ;; ZeroExt R1,R1,#+24,#+24
\ 00000010 4C1E SUBS R4,R1,#+1
\ 00000012 2300 MOVS R3,R4
521 tmpreg1 |= tmpreg2 << 13;
\ 00000014 52EA4332 ORRS R2,R2,R3, LSL #+13
522 /* Store the new register value */
523 ADCx->CR1 = tmpreg1;
\ 00000018 4260 STR R2,[R0, #+4]
524 }
\ 0000001A 10BC POP {R4}
\ 0000001C 7047 BX LR ;; return
525
526 /**
527 * @brief Enables or disables the discontinuous mode on regular group
528 * channel for the specified ADC
529 * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
530 * @param NewState: new state of the selected ADC discontinuous mode
531 * on regular group channel.
532 * This parameter can be: ENABLE or DISABLE.
533 * @retval None
534 */
\ In section .text, align 2, keep-with-next
535 void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
536 {
537 /* Check the parameters */
538 assert_param(IS_ADC_ALL_PERIPH(ADCx));
539 assert_param(IS_FUNCTIONAL_STATE(NewState));
540 if (NewState != DISABLE)
\ ADC_DiscModeCmd:
\ 00000000 C9B2 UXTB R1,R1 ;; ZeroExt R1,R1,#+24,#+24
\ 00000002 0029 CMP R1,#+0
\ 00000004 04D0 BEQ.N ??ADC_DiscModeCmd_0
541 {
542 /* Enable the selected ADC regular discontinuous mode */
543 ADCx->CR1 |= CR1_DISCEN_Set;
\ 00000006 4268 LDR R2,[R0, #+4]
\ 00000008 52F40062 ORRS R2,R2,#0x800
\ 0000000C 4260 STR R2,[R0, #+4]
\ 0000000E 03E0 B.N ??ADC_DiscModeCmd_1
544 }
545 else
546 {
547 /* Disable the selected ADC regular discontinuous mode */
548 ADCx->CR1 &= CR1_DISCEN_Reset;
\ ??ADC_DiscModeCmd_0:
\ 00000010 4268 LDR R2,[R0, #+4]
\ 00000012 32F40062 BICS R2,R2,#0x800
\ 00000016 4260 STR R2,[R0, #+4]
549 }
550 }
\ ??ADC_DiscModeCmd_1:
\ 00000018 7047 BX LR ;; return
551
552 /**
553 * @brief Configures for the selected ADC regular channel its corresponding
554 * rank in the sequencer and its sample time.
555 * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
556 * @param ADC_Channel: the ADC channel to configure.
557 * This parameter can be one of the following values:
558 * @arg ADC_Channel_0: ADC Channel0 selected
559 * @arg ADC_Channel_1: ADC Channel1 selected
560 * @arg ADC_Channel_2: ADC Channel2 selected
561 * @arg ADC_Channel_3: ADC Channel3 selected
562 * @arg ADC_Channel_4: ADC Channel4 selected
563 * @arg ADC_Channel_5: ADC Channel5 selected
564 * @arg ADC_Channel_6: ADC Channel6 selected
565 * @arg ADC_Channel_7: ADC Channel7 selected
566 * @arg ADC_Channel_8: ADC Channel8 selected
567 * @arg ADC_Channel_9: ADC Channel9 selected
568 * @arg ADC_Channel_10: ADC Channel10 selected
569 * @arg ADC_Channel_11: ADC Channel11 selected
570 * @arg ADC_Channel_12: ADC Channel12 selected
571 * @arg ADC_Channel_13: ADC Channel13 selected
572 * @arg ADC_Channel_14: ADC Channel14 selected
573 * @arg ADC_Channel_15: ADC Channel15 selected
574 * @arg ADC_Channel_16: ADC Channel16 selected
575 * @arg ADC_Channel_17: ADC Channel17 selected
576 * @param Rank: The rank in the regular group sequencer. This parameter must be between 1 to 16.
577 * @param ADC_SampleTime: The sample time value to be set for the selected channel.
578 * This parameter can be one of the following values:
579 * @arg ADC_SampleTime_1Cycles5: Sample time equal to 1.5 cycles
580 * @arg ADC_SampleTime_7Cycles5: Sample time equal to 7.5 cycles
581 * @arg ADC_SampleTime_13Cycles5: Sample time equal to 13.5 cycles
582 * @arg ADC_SampleTime_28Cycles5: Sample time equal to 28.5 cycles
583 * @arg ADC_SampleTime_41Cycles5: Sample time equal to 41.5 cycles
584 * @arg ADC_SampleTime_55Cycles5: Sample time equal to 55.5 cycles
585 * @arg ADC_SampleTime_71Cycles5: Sample time equal to 71.5 cycles
586 * @arg ADC_SampleTime_239Cycles5: Sample time equal to 239.5 cycles
587 * @retval None
588 */
\ In section .text, align 2, keep-with-next
589 void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
590 {
\ ADC_RegularChannelConfig:
\ 00000000 F0B4 PUSH {R4-R7}
591 uint32_t tmpreg1 = 0, tmpreg2 = 0;
\ 00000002 0025 MOVS R5,#+0
\ 00000004 0024 MOVS R4,#+0
592 /* Check the parameters */
593 assert_param(IS_ADC_ALL_PERIPH(ADCx));
594 assert_param(IS_ADC_CHANNEL(ADC_Channel));
595 assert_param(IS_ADC_REGULAR_RANK(Rank));
596 assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime));
597 /* if ADC_Channel_10 ... ADC_Channel_17 is selected */
598 if (ADC_Channel > ADC_Channel_9)
\ 00000006 C9B2 UXTB R1,R1 ;; ZeroExt R1,R1,#+24,#+24
\ 00000008 0A29 CMP R1,#+10
\ 0000000A 16D3 BCC.N ??ADC_RegularChannelConfig_0
599 {
600 /* Get the old register value */
601 tmpreg1 = ADCx->SMPR1;
\ 0000000C C668 LDR R6,[R0, #+12]
\ 0000000E 3500 MOVS R5,R6
602 /* Calculate the mask to clear */
603 tmpreg2 = SMPR1_SMP_Set << (3 * (ADC_Channel - 10));
\ 00000010 0726 MOVS R6,#+7
\ 00000012 B1F10A07 SUBS R7,R1,#+10
\ 00000016 5FF0030C MOVS R12,#+3
\ 0000001A 0CFB07F7 MUL R7,R12,R7
\ 0000001E BE40 LSLS R6,R6,R7
\ 00000020 3400 MOVS R4,R6
604 /* Clear the old channel sample time */
605 tmpreg1 &= ~tmpreg2;
\ 00000022 A543 BICS R5,R5,R4
606 /* Calculate the mask to set */
607 tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10));
\ 00000024 DBB2 UXTB R3,R3 ;; ZeroExt R3,R3,#+24,#+24
\ 00000026 B1F10A06 SUBS R6,R1,#+10
\ 0000002A 0327 MOVS R7,#+3
\ 0000002C 7E43 MULS R6,R7,R6
\ 0000002E 13FA06F6 LSLS R6,R3,R6
\ 00000032 3400 MOVS R4,R6
608 /* Set the new channel sample time */
609 tmpreg1 |= tmpreg2;
\ 00000034 2543 ORRS R5,R4,R5
610 /* Store the new register value */
611 ADCx->SMPR1 = tmpreg1;
\ 00000036 C560 STR R5,[R0, #+12]
\ 00000038 11E0 B.N ??ADC_RegularChannelConfig_1
612 }
613 else /* ADC_Channel include in ADC_Channel_[0..9] */
614 {
615 /* Get the old register value */
616 tmpreg1 = ADCx->SMPR2;
\ ??ADC_RegularChannelConfig_0:
\ 0000003A 0669 LDR R6,[R0, #+16]
\ 0000003C 3500 MOVS R5,R6
617 /* Calculate the mask to clear */
618 tmpreg2 = SMPR2_SMP_Set << (3 * ADC_Channel);
\ 0000003E 0726 MOVS R6,#+7
\ 00000040 0327 MOVS R7,#+3
\ 00000042 07FB01F7 MUL R7,R7,R1
\ 00000046 BE40 LSLS R6,R6,R7
\ 00000048 3400 MOVS R4,R6
619 /* Clear the old channel sample time */
620 tmpreg1 &= ~tmpreg2;
\ 0000004A A543 BICS R5,R5,R4
621 /* Calculate the mask to set */
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