📄 stm32f10x_adc.lst
字号:
###############################################################################
# #
# IAR ANSI C/C++ Compiler V6.10.2.52244/W32 for ARM 07/Aug/2011 12:10:32 #
# Copyright 1999-2010 IAR Systems AB. #
# #
# Cpu mode = thumb #
# Endian = little #
# Source file = F:\stm32\我的程序\Micrium\Software\EWARM\BSP\ST\STM32F10 #
# x_StdPeriph_Driver\src\stm32f10x_adc.c #
# Command line = F:\stm32\我的程序\Micrium\Software\EWARM\BSP\ST\STM32F10 #
# x_StdPeriph_Driver\src\stm32f10x_adc.c -D #
# USE_STDPERIPH_DRIVER -D STM32F10X_CL -lCN #
# F:\stm32\我的程序\Micrium\Software\EWARM\OS-II\Flash\Lis #
# t\ -o F:\stm32\我的程序\Micrium\Software\EWARM\OS-II\Fla #
# sh\Obj\ --no_cse --no_unroll --no_inline #
# --no_code_motion --no_tbaa --no_clustering #
# --no_scheduling --debug --endian=little --cpu=Cortex-M3 #
# -e --fpu=None --dlib_config #
# D:\arm\INC\c\DLib_Config_Normal.h -I #
# F:\stm32\我的程序\Micrium\Software\EWARM\OS-II\APP\ -I #
# F:\stm32\我的程序\Micrium\Software\EWARM\OS-II\..\BSP\ #
# -I F:\stm32\我的程序\Micrium\Software\EWARM\OS-II\..\BSP #
# \ST\CMSIS\CM3\CoreSupport\ -I #
# F:\stm32\我的程序\Micrium\Software\EWARM\OS-II\..\BSP\ST #
# \CMSIS\CM3\DeviceSupport\ST\STM32F10x\ -I #
# F:\stm32\我的程序\Micrium\Software\EWARM\OS-II\..\BSP\ST #
# \STM32F10x_StdPeriph_Driver\inc\ -I #
# F:\stm32\我的程序\Micrium\Software\EWARM\OS-II\..\BSP\uC #
# OS-II\ -I F:\stm32\我的程序\Micrium\Software\EWARM\OS-II #
# \..\..\uCOS-II\Ports\ARM-Cortex-M3\Generic\IAR\ -I #
# F:\stm32\我的程序\Micrium\Software\EWARM\OS-II\..\..\uCO #
# S-II\Source\ -I F:\stm32\我的程序\Micrium\Software\EWARM #
# \OS-II\..\..\uC-LIB\ -I F:\stm32\我的程序\Micrium\Softwa #
# re\EWARM\OS-II\..\..\uC-LIB\Ports\ARM-Cortex-M3\IAR\ -I #
# F:\stm32\我的程序\Micrium\Software\EWARM\OS-II\..\..\uC- #
# CPU\ -I F:\stm32\我的程序\Micrium\Software\EWARM\OS-II\. #
# .\..\uC-CPU\ARM-Cortex-M3\IAR\ -On --use_c++_inline #
# List file = F:\stm32\我的程序\Micrium\Software\EWARM\OS-II\Flash\Lis #
# t\stm32f10x_adc.lst #
# Object file = F:\stm32\我的程序\Micrium\Software\EWARM\OS-II\Flash\Obj #
# \stm32f10x_adc.o #
# #
# #
###############################################################################
F:\stm32\我的程序\Micrium\Software\EWARM\BSP\ST\STM32F10x_StdPeriph_Driver\src\stm32f10x_adc.c
1 /**
2 ******************************************************************************
3 * @file stm32f10x_adc.c
4 * @author MCD Application Team
5 * @version V3.4.0
6 * @date 10/15/2010
7 * @brief This file provides all the ADC firmware functions.
8 ******************************************************************************
9 * @copy
10 *
11 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
12 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
13 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
14 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
15 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
16 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
17 *
18 * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
19 */
20
21 /* Includes ------------------------------------------------------------------*/
22 #include "stm32f10x_adc.h"
23 #include "stm32f10x_rcc.h"
24
25 /** @addtogroup STM32F10x_StdPeriph_Driver
26 * @{
27 */
28
29 /** @defgroup ADC
30 * @brief ADC driver modules
31 * @{
32 */
33
34 /** @defgroup ADC_Private_TypesDefinitions
35 * @{
36 */
37
38 /**
39 * @}
40 */
41
42 /** @defgroup ADC_Private_Defines
43 * @{
44 */
45
46 /* ADC DISCNUM mask */
47 #define CR1_DISCNUM_Reset ((uint32_t)0xFFFF1FFF)
48
49 /* ADC DISCEN mask */
50 #define CR1_DISCEN_Set ((uint32_t)0x00000800)
51 #define CR1_DISCEN_Reset ((uint32_t)0xFFFFF7FF)
52
53 /* ADC JAUTO mask */
54 #define CR1_JAUTO_Set ((uint32_t)0x00000400)
55 #define CR1_JAUTO_Reset ((uint32_t)0xFFFFFBFF)
56
57 /* ADC JDISCEN mask */
58 #define CR1_JDISCEN_Set ((uint32_t)0x00001000)
59 #define CR1_JDISCEN_Reset ((uint32_t)0xFFFFEFFF)
60
61 /* ADC AWDCH mask */
62 #define CR1_AWDCH_Reset ((uint32_t)0xFFFFFFE0)
63
64 /* ADC Analog watchdog enable mode mask */
65 #define CR1_AWDMode_Reset ((uint32_t)0xFF3FFDFF)
66
67 /* CR1 register Mask */
68 #define CR1_CLEAR_Mask ((uint32_t)0xFFF0FEFF)
69
70 /* ADC ADON mask */
71 #define CR2_ADON_Set ((uint32_t)0x00000001)
72 #define CR2_ADON_Reset ((uint32_t)0xFFFFFFFE)
73
74 /* ADC DMA mask */
75 #define CR2_DMA_Set ((uint32_t)0x00000100)
76 #define CR2_DMA_Reset ((uint32_t)0xFFFFFEFF)
77
78 /* ADC RSTCAL mask */
79 #define CR2_RSTCAL_Set ((uint32_t)0x00000008)
80
81 /* ADC CAL mask */
82 #define CR2_CAL_Set ((uint32_t)0x00000004)
83
84 /* ADC SWSTART mask */
85 #define CR2_SWSTART_Set ((uint32_t)0x00400000)
86
87 /* ADC EXTTRIG mask */
88 #define CR2_EXTTRIG_Set ((uint32_t)0x00100000)
89 #define CR2_EXTTRIG_Reset ((uint32_t)0xFFEFFFFF)
90
91 /* ADC Software start mask */
92 #define CR2_EXTTRIG_SWSTART_Set ((uint32_t)0x00500000)
93 #define CR2_EXTTRIG_SWSTART_Reset ((uint32_t)0xFFAFFFFF)
94
95 /* ADC JEXTSEL mask */
96 #define CR2_JEXTSEL_Reset ((uint32_t)0xFFFF8FFF)
97
98 /* ADC JEXTTRIG mask */
99 #define CR2_JEXTTRIG_Set ((uint32_t)0x00008000)
100 #define CR2_JEXTTRIG_Reset ((uint32_t)0xFFFF7FFF)
101
102 /* ADC JSWSTART mask */
103 #define CR2_JSWSTART_Set ((uint32_t)0x00200000)
104
105 /* ADC injected software start mask */
106 #define CR2_JEXTTRIG_JSWSTART_Set ((uint32_t)0x00208000)
107 #define CR2_JEXTTRIG_JSWSTART_Reset ((uint32_t)0xFFDF7FFF)
108
109 /* ADC TSPD mask */
110 #define CR2_TSVREFE_Set ((uint32_t)0x00800000)
111 #define CR2_TSVREFE_Reset ((uint32_t)0xFF7FFFFF)
112
113 /* CR2 register Mask */
114 #define CR2_CLEAR_Mask ((uint32_t)0xFFF1F7FD)
115
116 /* ADC SQx mask */
117 #define SQR3_SQ_Set ((uint32_t)0x0000001F)
118 #define SQR2_SQ_Set ((uint32_t)0x0000001F)
119 #define SQR1_SQ_Set ((uint32_t)0x0000001F)
120
121 /* SQR1 register Mask */
122 #define SQR1_CLEAR_Mask ((uint32_t)0xFF0FFFFF)
123
124 /* ADC JSQx mask */
125 #define JSQR_JSQ_Set ((uint32_t)0x0000001F)
126
127 /* ADC JL mask */
128 #define JSQR_JL_Set ((uint32_t)0x00300000)
129 #define JSQR_JL_Reset ((uint32_t)0xFFCFFFFF)
130
131 /* ADC SMPx mask */
132 #define SMPR1_SMP_Set ((uint32_t)0x00000007)
133 #define SMPR2_SMP_Set ((uint32_t)0x00000007)
134
135 /* ADC JDRx registers offset */
136 #define JDR_Offset ((uint8_t)0x28)
137
138 /* ADC1 DR register base address */
139 #define DR_ADDRESS ((uint32_t)0x4001244C)
140
141 /**
142 * @}
143 */
144
145 /** @defgroup ADC_Private_Macros
146 * @{
147 */
148
149 /**
150 * @}
151 */
152
153 /** @defgroup ADC_Private_Variables
154 * @{
155 */
156
157 /**
158 * @}
159 */
160
161 /** @defgroup ADC_Private_FunctionPrototypes
162 * @{
163 */
164
165 /**
166 * @}
167 */
168
169 /** @defgroup ADC_Private_Functions
170 * @{
171 */
172
173 /**
174 * @brief Deinitializes the ADCx peripheral registers to their default reset values.
175 * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
176 * @retval None
177 */
\ In section .text, align 2, keep-with-next
178 void ADC_DeInit(ADC_TypeDef* ADCx)
179 {
\ ADC_DeInit:
\ 00000000 10B5 PUSH {R4,LR}
\ 00000002 0400 MOVS R4,R0
180 /* Check the parameters */
181 assert_param(IS_ADC_ALL_PERIPH(ADCx));
182
183 if (ADCx == ADC1)
\ 00000004 ........ LDR.W R0,??DataTable4 ;; 0x40012400
\ 00000008 8442 CMP R4,R0
\ 0000000A 0AD1 BNE.N ??ADC_DeInit_0
184 {
185 /* Enable ADC1 reset state */
186 RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, ENABLE);
\ 0000000C 0121 MOVS R1,#+1
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -