stm32f10x_sdio.lst
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\ 00000022 0160 STR R1,[R0, #+0]
168 SDIO->DCTRL = 0x00000000;
\ 00000024 .... LDR.N R0,??DataTable26_6 ;; 0x4001802c
\ 00000026 0021 MOVS R1,#+0
\ 00000028 0160 STR R1,[R0, #+0]
169 SDIO->ICR = 0x00C007FF;
\ 0000002A .... LDR.N R0,??DataTable26_7 ;; 0x40018038
\ 0000002C .... LDR.N R1,??DataTable26_8 ;; 0xc007ff
\ 0000002E 0160 STR R1,[R0, #+0]
170 SDIO->MASK = 0x00000000;
\ 00000030 .... LDR.N R0,??DataTable26_9 ;; 0x4001803c
\ 00000032 0021 MOVS R1,#+0
\ 00000034 0160 STR R1,[R0, #+0]
171 }
\ 00000036 7047 BX LR ;; return
172
173 /**
174 * @brief Initializes the SDIO peripheral according to the specified
175 * parameters in the SDIO_InitStruct.
176 * @param SDIO_InitStruct : pointer to a SDIO_InitTypeDef structure
177 * that contains the configuration information for the SDIO peripheral.
178 * @retval None
179 */
\ In section .text, align 2, keep-with-next
180 void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct)
181 {
182 uint32_t tmpreg = 0;
\ SDIO_Init:
\ 00000000 0021 MOVS R1,#+0
183
184 /* Check the parameters */
185 assert_param(IS_SDIO_CLOCK_EDGE(SDIO_InitStruct->SDIO_ClockEdge));
186 assert_param(IS_SDIO_CLOCK_BYPASS(SDIO_InitStruct->SDIO_ClockBypass));
187 assert_param(IS_SDIO_CLOCK_POWER_SAVE(SDIO_InitStruct->SDIO_ClockPowerSave));
188 assert_param(IS_SDIO_BUS_WIDE(SDIO_InitStruct->SDIO_BusWide));
189 assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(SDIO_InitStruct->SDIO_HardwareFlowControl));
190
191 /*---------------------------- SDIO CLKCR Configuration ------------------------*/
192 /* Get the SDIO CLKCR value */
193 tmpreg = SDIO->CLKCR;
\ 00000002 .... LDR.N R2,??DataTable26_1 ;; 0x40018004
\ 00000004 1268 LDR R2,[R2, #+0]
\ 00000006 1100 MOVS R1,R2
194
195 /* Clear CLKDIV, PWRSAV, BYPASS, WIDBUS, NEGEDGE, HWFC_EN bits */
196 tmpreg &= CLKCR_CLEAR_MASK;
\ 00000008 .... LDR.N R2,??DataTable26_10 ;; 0xffff8100
\ 0000000A 1140 ANDS R1,R2,R1
197
198 /* Set CLKDIV bits according to SDIO_ClockDiv value */
199 /* Set PWRSAV bit according to SDIO_ClockPowerSave value */
200 /* Set BYPASS bit according to SDIO_ClockBypass value */
201 /* Set WIDBUS bits according to SDIO_BusWide value */
202 /* Set NEGEDGE bits according to SDIO_ClockEdge value */
203 /* Set HWFC_EN bits according to SDIO_HardwareFlowControl value */
204 tmpreg |= (SDIO_InitStruct->SDIO_ClockDiv | SDIO_InitStruct->SDIO_ClockPowerSave |
205 SDIO_InitStruct->SDIO_ClockBypass | SDIO_InitStruct->SDIO_BusWide |
206 SDIO_InitStruct->SDIO_ClockEdge | SDIO_InitStruct->SDIO_HardwareFlowControl);
\ 0000000C 027D LDRB R2,[R0, #+20]
\ 0000000E 8368 LDR R3,[R0, #+8]
\ 00000010 1A43 ORRS R2,R3,R2
\ 00000012 4368 LDR R3,[R0, #+4]
\ 00000014 1A43 ORRS R2,R3,R2
\ 00000016 C368 LDR R3,[R0, #+12]
\ 00000018 1A43 ORRS R2,R3,R2
\ 0000001A 0368 LDR R3,[R0, #+0]
\ 0000001C 1A43 ORRS R2,R3,R2
\ 0000001E 0369 LDR R3,[R0, #+16]
\ 00000020 1A43 ORRS R2,R3,R2
\ 00000022 1143 ORRS R1,R2,R1
207
208 /* Write to SDIO CLKCR */
209 SDIO->CLKCR = tmpreg;
\ 00000024 .... LDR.N R2,??DataTable26_1 ;; 0x40018004
\ 00000026 1160 STR R1,[R2, #+0]
210 }
\ 00000028 7047 BX LR ;; return
211
212 /**
213 * @brief Fills each SDIO_InitStruct member with its default value.
214 * @param SDIO_InitStruct: pointer to an SDIO_InitTypeDef structure which
215 * will be initialized.
216 * @retval None
217 */
\ In section .text, align 2, keep-with-next
218 void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct)
219 {
220 /* SDIO_InitStruct members default value */
221 SDIO_InitStruct->SDIO_ClockDiv = 0x00;
\ SDIO_StructInit:
\ 00000000 0021 MOVS R1,#+0
\ 00000002 0175 STRB R1,[R0, #+20]
222 SDIO_InitStruct->SDIO_ClockEdge = SDIO_ClockEdge_Rising;
\ 00000004 0021 MOVS R1,#+0
\ 00000006 0160 STR R1,[R0, #+0]
223 SDIO_InitStruct->SDIO_ClockBypass = SDIO_ClockBypass_Disable;
\ 00000008 0021 MOVS R1,#+0
\ 0000000A 4160 STR R1,[R0, #+4]
224 SDIO_InitStruct->SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable;
\ 0000000C 0021 MOVS R1,#+0
\ 0000000E 8160 STR R1,[R0, #+8]
225 SDIO_InitStruct->SDIO_BusWide = SDIO_BusWide_1b;
\ 00000010 0021 MOVS R1,#+0
\ 00000012 C160 STR R1,[R0, #+12]
226 SDIO_InitStruct->SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable;
\ 00000014 0021 MOVS R1,#+0
\ 00000016 0161 STR R1,[R0, #+16]
227 }
\ 00000018 7047 BX LR ;; return
228
229 /**
230 * @brief Enables or disables the SDIO Clock.
231 * @param NewState: new state of the SDIO Clock. This parameter can be: ENABLE or DISABLE.
232 * @retval None
233 */
\ In section .text, align 2, keep-with-next
234 void SDIO_ClockCmd(FunctionalState NewState)
235 {
236 /* Check the parameters */
237 assert_param(IS_FUNCTIONAL_STATE(NewState));
238
239 *(__IO uint32_t *) CLKCR_CLKEN_BB = (uint32_t)NewState;
\ SDIO_ClockCmd:
\ 00000000 .... LDR.N R1,??DataTable26_11 ;; 0x423000a0
\ 00000002 C0B2 UXTB R0,R0 ;; ZeroExt R0,R0,#+24,#+24
\ 00000004 0860 STR R0,[R1, #+0]
240 }
\ 00000006 7047 BX LR ;; return
241
242 /**
243 * @brief Sets the power status of the controller.
244 * @param SDIO_PowerState: new state of the Power state.
245 * This parameter can be one of the following values:
246 * @arg SDIO_PowerState_OFF
247 * @arg SDIO_PowerState_ON
248 * @retval None
249 */
\ In section .text, align 2, keep-with-next
250 void SDIO_SetPowerState(uint32_t SDIO_PowerState)
251 {
252 /* Check the parameters */
253 assert_param(IS_SDIO_POWER_STATE(SDIO_PowerState));
254
255 SDIO->POWER &= PWR_PWRCTRL_MASK;
\ SDIO_SetPowerState:
\ 00000000 .... LDR.N R1,??DataTable26 ;; 0x40018000
\ 00000002 0968 LDR R1,[R1, #+0]
\ 00000004 8908 LSRS R1,R1,#+2
\ 00000006 8900 LSLS R1,R1,#+2
\ 00000008 .... LDR.N R2,??DataTable26 ;; 0x40018000
\ 0000000A 1160 STR R1,[R2, #+0]
256 SDIO->POWER |= SDIO_PowerState;
\ 0000000C .... LDR.N R1,??DataTable26 ;; 0x40018000
\ 0000000E 0968 LDR R1,[R1, #+0]
\ 00000010 0143 ORRS R1,R0,R1
\ 00000012 .... LDR.N R2,??DataTable26 ;; 0x40018000
\ 00000014 1160 STR R1,[R2, #+0]
257 }
\ 00000016 7047 BX LR ;; return
258
259 /**
260 * @brief Gets the power status of the controller.
261 * @param None
262 * @retval Power status of the controller. The returned value can
263 * be one of the following:
264 * - 0x00: Power OFF
265 * - 0x02: Power UP
266 * - 0x03: Power ON
267 */
\ In section .text, align 2, keep-with-next
268 uint32_t SDIO_GetPowerState(void)
269 {
270 return (SDIO->POWER & (~PWR_PWRCTRL_MASK));
\ SDIO_GetPowerState:
\ 00000000 .... LDR.N R0,??DataTable26 ;; 0x40018000
\ 00000002 0068 LDR R0,[R0, #+0]
\ 00000004 10F00300 ANDS R0,R0,#0x3
\ 00000008 7047 BX LR ;; return
271 }
272
273 /**
274 * @brief Enables or disables the SDIO interrupts.
275 * @param SDIO_IT: specifies the SDIO interrupt sources to be enabled or disabled.
276 * This parameter can be one or a combination of the following values:
277 * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
278 * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
279 * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
280 * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
281 * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
282 * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
283 * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
284 * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
285 * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
286 * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
287 * bus mode interrupt
288 * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
289 * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
290 * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
291 * @arg SDIO_IT_RXACT: Data receive in progress interrupt
292 * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
293 * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
294 * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
295 * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
296 * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
297 * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
298 * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
299 * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
300 * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
301 * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
302 * @param NewState: new state of the specified SDIO interrupts.
303 * This parameter can be: ENABLE or DISABLE.
304 * @retval None
305 */
\ In section .text, align 2, keep-with-next
306 void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState)
307 {
308 /* Check the parameters */
309 assert_param(IS_SDIO_IT(SDIO_IT));
310 assert_param(IS_FUNCTIONAL_STATE(NewState));
311
312 if (NewState != DISABLE)
\ SDIO_ITConfig:
\ 00000000 C9B2 UXTB R1,R1 ;; ZeroExt R1,R1,#+24,#+24
\ 00000002 0029 CMP R1,#+0
\ 00000004 05D0 BEQ.N ??SDIO_ITConfig_0
313 {
314 /* Enable the SDIO interrupts */
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