📄 stm32f10x_rcc.lst
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\ 00000014 1160 STR R1,[R2, #+0]
645 }
\ 00000016 7047 BX LR ;; return
646
647 /**
648 * @brief Configures the High Speed APB clock (PCLK2).
649 * @param RCC_HCLK: defines the APB2 clock divider. This clock is derived from
650 * the AHB clock (HCLK).
651 * This parameter can be one of the following values:
652 * @arg RCC_HCLK_Div1: APB2 clock = HCLK
653 * @arg RCC_HCLK_Div2: APB2 clock = HCLK/2
654 * @arg RCC_HCLK_Div4: APB2 clock = HCLK/4
655 * @arg RCC_HCLK_Div8: APB2 clock = HCLK/8
656 * @arg RCC_HCLK_Div16: APB2 clock = HCLK/16
657 * @retval None
658 */
\ In section .text, align 2, keep-with-next
659 void RCC_PCLK2Config(uint32_t RCC_HCLK)
660 {
661 uint32_t tmpreg = 0;
\ RCC_PCLK2Config:
\ 00000000 0021 MOVS R1,#+0
662 /* Check the parameters */
663 assert_param(IS_RCC_PCLK(RCC_HCLK));
664 tmpreg = RCC->CFGR;
\ 00000002 ........ LDR.W R2,??DataTable39_1 ;; 0x40021004
\ 00000006 1268 LDR R2,[R2, #+0]
\ 00000008 1100 MOVS R1,R2
665 /* Clear PPRE2[2:0] bits */
666 tmpreg &= CFGR_PPRE2_Reset_Mask;
\ 0000000A 31F46051 BICS R1,R1,#0x3800
667 /* Set PPRE2[2:0] bits according to RCC_HCLK value */
668 tmpreg |= RCC_HCLK << 3;
\ 0000000E 51EAC001 ORRS R1,R1,R0, LSL #+3
669 /* Store the new value */
670 RCC->CFGR = tmpreg;
\ 00000012 ........ LDR.W R2,??DataTable39_1 ;; 0x40021004
\ 00000016 1160 STR R1,[R2, #+0]
671 }
\ 00000018 7047 BX LR ;; return
672
673 /**
674 * @brief Enables or disables the specified RCC interrupts.
675 * @param RCC_IT: specifies the RCC interrupt sources to be enabled or disabled.
676 *
677 * For @b STM32_Connectivity_line_devices, this parameter can be any combination
678 * of the following values
679 * @arg RCC_IT_LSIRDY: LSI ready interrupt
680 * @arg RCC_IT_LSERDY: LSE ready interrupt
681 * @arg RCC_IT_HSIRDY: HSI ready interrupt
682 * @arg RCC_IT_HSERDY: HSE ready interrupt
683 * @arg RCC_IT_PLLRDY: PLL ready interrupt
684 * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt
685 * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt
686 *
687 * For @b other_STM32_devices, this parameter can be any combination of the
688 * following values
689 * @arg RCC_IT_LSIRDY: LSI ready interrupt
690 * @arg RCC_IT_LSERDY: LSE ready interrupt
691 * @arg RCC_IT_HSIRDY: HSI ready interrupt
692 * @arg RCC_IT_HSERDY: HSE ready interrupt
693 * @arg RCC_IT_PLLRDY: PLL ready interrupt
694 *
695 * @param NewState: new state of the specified RCC interrupts.
696 * This parameter can be: ENABLE or DISABLE.
697 * @retval None
698 */
\ In section .text, align 2, keep-with-next
699 void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState)
700 {
701 /* Check the parameters */
702 assert_param(IS_RCC_IT(RCC_IT));
703 assert_param(IS_FUNCTIONAL_STATE(NewState));
704 if (NewState != DISABLE)
\ RCC_ITConfig:
\ 00000000 C9B2 UXTB R1,R1 ;; ZeroExt R1,R1,#+24,#+24
\ 00000002 0029 CMP R1,#+0
\ 00000004 07D0 BEQ.N ??RCC_ITConfig_0
705 {
706 /* Perform Byte access to RCC_CIR bits to enable the selected interrupts */
707 *(__IO uint8_t *) CIR_BYTE2_ADDRESS |= RCC_IT;
\ 00000006 ........ LDR.W R2,??DataTable39_11 ;; 0x40021009
\ 0000000A 1278 LDRB R2,[R2, #+0]
\ 0000000C 0243 ORRS R2,R0,R2
\ 0000000E ........ LDR.W R3,??DataTable39_11 ;; 0x40021009
\ 00000012 1A70 STRB R2,[R3, #+0]
\ 00000014 06E0 B.N ??RCC_ITConfig_1
708 }
709 else
710 {
711 /* Perform Byte access to RCC_CIR bits to disable the selected interrupts */
712 *(__IO uint8_t *) CIR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT;
\ ??RCC_ITConfig_0:
\ 00000016 ........ LDR.W R2,??DataTable39_11 ;; 0x40021009
\ 0000001A 1278 LDRB R2,[R2, #+0]
\ 0000001C 8243 BICS R2,R2,R0
\ 0000001E ........ LDR.W R3,??DataTable39_11 ;; 0x40021009
\ 00000022 1A70 STRB R2,[R3, #+0]
713 }
714 }
\ ??RCC_ITConfig_1:
\ 00000024 7047 BX LR ;; return
715
716 #ifndef STM32F10X_CL
717 /**
718 * @brief Configures the USB clock (USBCLK).
719 * @param RCC_USBCLKSource: specifies the USB clock source. This clock is
720 * derived from the PLL output.
721 * This parameter can be one of the following values:
722 * @arg RCC_USBCLKSource_PLLCLK_1Div5: PLL clock divided by 1,5 selected as USB
723 * clock source
724 * @arg RCC_USBCLKSource_PLLCLK_Div1: PLL clock selected as USB clock source
725 * @retval None
726 */
727 void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource)
728 {
729 /* Check the parameters */
730 assert_param(IS_RCC_USBCLK_SOURCE(RCC_USBCLKSource));
731
732 *(__IO uint32_t *) CFGR_USBPRE_BB = RCC_USBCLKSource;
733 }
734 #else
735 /**
736 * @brief Configures the USB OTG FS clock (OTGFSCLK).
737 * This function applies only to STM32 Connectivity line devices.
738 * @param RCC_OTGFSCLKSource: specifies the USB OTG FS clock source.
739 * This clock is derived from the PLL output.
740 * This parameter can be one of the following values:
741 * @arg RCC_OTGFSCLKSource_PLLVCO_Div3: PLL VCO clock divided by 2 selected as USB OTG FS clock source
742 * @arg RCC_OTGFSCLKSource_PLLVCO_Div2: PLL VCO clock divided by 2 selected as USB OTG FS clock source
743 * @retval None
744 */
\ In section .text, align 2, keep-with-next
745 void RCC_OTGFSCLKConfig(uint32_t RCC_OTGFSCLKSource)
746 {
747 /* Check the parameters */
748 assert_param(IS_RCC_OTGFSCLK_SOURCE(RCC_OTGFSCLKSource));
749
750 *(__IO uint32_t *) CFGR_OTGFSPRE_BB = RCC_OTGFSCLKSource;
\ RCC_OTGFSCLKConfig:
\ 00000000 ........ LDR.W R1,??DataTable39_12 ;; 0x424200d8
\ 00000004 0860 STR R0,[R1, #+0]
751 }
\ 00000006 7047 BX LR ;; return
752 #endif /* STM32F10X_CL */
753
754 /**
755 * @brief Configures the ADC clock (ADCCLK).
756 * @param RCC_PCLK2: defines the ADC clock divider. This clock is derived from
757 * the APB2 clock (PCLK2).
758 * This parameter can be one of the following values:
759 * @arg RCC_PCLK2_Div2: ADC clock = PCLK2/2
760 * @arg RCC_PCLK2_Div4: ADC clock = PCLK2/4
761 * @arg RCC_PCLK2_Div6: ADC clock = PCLK2/6
762 * @arg RCC_PCLK2_Div8: ADC clock = PCLK2/8
763 * @retval None
764 */
\ In section .text, align 2, keep-with-next
765 void RCC_ADCCLKConfig(uint32_t RCC_PCLK2)
766 {
767 uint32_t tmpreg = 0;
\ RCC_ADCCLKConfig:
\ 00000000 0021 MOVS R1,#+0
768 /* Check the parameters */
769 assert_param(IS_RCC_ADCCLK(RCC_PCLK2));
770 tmpreg = RCC->CFGR;
\ 00000002 ........ LDR.W R2,??DataTable39_1 ;; 0x40021004
\ 00000006 1268 LDR R2,[R2, #+0]
\ 00000008 1100 MOVS R1,R2
771 /* Clear ADCPRE[1:0] bits */
772 tmpreg &= CFGR_ADCPRE_Reset_Mask;
\ 0000000A 31F44041 BICS R1,R1,#0xC000
773 /* Set ADCPRE[1:0] bits according to RCC_PCLK2 value */
774 tmpreg |= RCC_PCLK2;
\ 0000000E 0143 ORRS R1,R0,R1
775 /* Store the new value */
776 RCC->CFGR = tmpreg;
\ 00000010 ........ LDR.W R2,??DataTable39_1 ;; 0x40021004
\ 00000014 1160 STR R1,[R2, #+0]
777 }
\ 00000016 7047 BX LR ;; return
778
779 #ifdef STM32F10X_CL
780 /**
781 * @brief Configures the I2S2 clock source(I2S2CLK).
782 * @note
783 * - This function must be called before enabling I2S2 APB clock.
784 * - This function applies only to STM32 Connectivity line devices.
785 * @param RCC_I2S2CLKSource: specifies the I2S2 clock source.
786 * This parameter can be one of the following values:
787 * @arg RCC_I2S2CLKSource_SYSCLK: system clock selected as I2S2 clock entry
788 * @arg RCC_I2S2CLKSource_PLL3_VCO: PLL3 VCO clock selected as I2S2 clock entry
789 * @retval None
790 */
\ In section .text, align 2, keep-with-next
791 void RCC_I2S2CLKConfig(uint32_t RCC_I2S2CLKSource)
792 {
793 /* Check the parameters */
794 assert_param(IS_RCC_I2S2CLK_SOURCE(RCC_I2S2CLKSource));
795
796 *(__IO uint32_t *) CFGR2_I2S2SRC_BB = RCC_I2S2CLKSource;
\ RCC_I2S2CLKConfig:
\ 00000000 ........ LDR.W R1,??DataTable39_13 ;; 0x424205c4
\ 00000004 0860 STR R0,[R1, #+0]
797 }
\ 00000006 7047 BX LR ;; return
798
799 /**
800 * @brief Configures the I2S3 clock source(I2S2CLK).
801 * @note
802 * - This function must be called before enabling I2S3 APB clock.
803 * - This function applies only to STM32 Connectivity line devices.
804 * @param RCC_I2S3CLKSource: specifies the I2S3 clock source.
805 * This parameter can be one of the following values:
806 * @arg RCC_I2S3CLKSource_SYSCLK: system clock selected as I2S3 clock entry
807 * @arg RCC_I2S3CLKSource_PLL3_VCO: PLL3 VCO clock selected as I2S3 clock entry
808 * @retval None
809 */
\ In section .text, align 2, keep-with-next
810 void RCC_I2S3CLKConfig(uint32_t RCC_I2S3CLKSource)
811 {
812 /* Check the parameters */
813 assert_param(IS_RCC_I2S3CLK_SOURCE(RCC_I2S3CLKSource));
814
815 *(__IO uint32_t *) CFGR2_I2S3SRC_BB = RCC_I2S3CLKSource;
\ RCC_I2S3CLKConfig:
\ 00000000 ........ LDR.W R1,??DataTable39_14 ;; 0x424205c8
\ 00000004 0860 STR R0,[R1, #+0]
816 }
\ 00000006 7047 BX LR ;; return
817 #endif /* STM32F10X_CL */
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