📄 stm32f10x_rcc.lst
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481
482 /* Check the parameters */
483 assert_param(IS_RCC_PLL2_MUL(RCC_PLL2Mul));
484
485 tmpreg = RCC->CFGR2;
\ 00000002 ........ LDR.W R2,??DataTable39_5 ;; 0x4002102c
\ 00000006 1268 LDR R2,[R2, #+0]
\ 00000008 1100 MOVS R1,R2
486 /* Clear PLL2Mul[3:0] bits */
487 tmpreg &= ~CFGR2_PLL2MUL;
\ 0000000A 31F47061 BICS R1,R1,#0xF00
488 /* Set the PLL2 configuration bits */
489 tmpreg |= RCC_PLL2Mul;
\ 0000000E 0143 ORRS R1,R0,R1
490 /* Store the new value */
491 RCC->CFGR2 = tmpreg;
\ 00000010 ........ LDR.W R2,??DataTable39_5 ;; 0x4002102c
\ 00000014 1160 STR R1,[R2, #+0]
492 }
\ 00000016 7047 BX LR ;; return
493
494
495 /**
496 * @brief Enables or disables the PLL2.
497 * @note
498 * - The PLL2 can not be disabled if it is used indirectly as system clock
499 * (i.e. it is used as PLL clock entry that is used as System clock).
500 * - This function applies only to STM32 Connectivity line devices.
501 * @param NewState: new state of the PLL2. This parameter can be: ENABLE or DISABLE.
502 * @retval None
503 */
\ In section .text, align 2, keep-with-next
504 void RCC_PLL2Cmd(FunctionalState NewState)
505 {
506 /* Check the parameters */
507 assert_param(IS_FUNCTIONAL_STATE(NewState));
508
509 *(__IO uint32_t *) CR_PLL2ON_BB = (uint32_t)NewState;
\ RCC_PLL2Cmd:
\ 00000000 ........ LDR.W R1,??DataTable39_9 ;; 0x42420068
\ 00000004 C0B2 UXTB R0,R0 ;; ZeroExt R0,R0,#+24,#+24
\ 00000006 0860 STR R0,[R1, #+0]
510 }
\ 00000008 7047 BX LR ;; return
511
512
513 /**
514 * @brief Configures the PLL3 multiplication factor.
515 * @note
516 * - This function must be used only when the PLL3 is disabled.
517 * - This function applies only to STM32 Connectivity line devices.
518 * @param RCC_PLL3Mul: specifies the PLL3 multiplication factor.
519 * This parameter can be RCC_PLL3Mul_x where x:{[8,14], 16, 20}
520 * @retval None
521 */
\ In section .text, align 2, keep-with-next
522 void RCC_PLL3Config(uint32_t RCC_PLL3Mul)
523 {
524 uint32_t tmpreg = 0;
\ RCC_PLL3Config:
\ 00000000 0021 MOVS R1,#+0
525
526 /* Check the parameters */
527 assert_param(IS_RCC_PLL3_MUL(RCC_PLL3Mul));
528
529 tmpreg = RCC->CFGR2;
\ 00000002 ........ LDR.W R2,??DataTable39_5 ;; 0x4002102c
\ 00000006 1268 LDR R2,[R2, #+0]
\ 00000008 1100 MOVS R1,R2
530 /* Clear PLL3Mul[3:0] bits */
531 tmpreg &= ~CFGR2_PLL3MUL;
\ 0000000A 31F47041 BICS R1,R1,#0xF000
532 /* Set the PLL3 configuration bits */
533 tmpreg |= RCC_PLL3Mul;
\ 0000000E 0143 ORRS R1,R0,R1
534 /* Store the new value */
535 RCC->CFGR2 = tmpreg;
\ 00000010 ........ LDR.W R2,??DataTable39_5 ;; 0x4002102c
\ 00000014 1160 STR R1,[R2, #+0]
536 }
\ 00000016 7047 BX LR ;; return
537
538
539 /**
540 * @brief Enables or disables the PLL3.
541 * @note This function applies only to STM32 Connectivity line devices.
542 * @param NewState: new state of the PLL3. This parameter can be: ENABLE or DISABLE.
543 * @retval None
544 */
\ In section .text, align 2, keep-with-next
545 void RCC_PLL3Cmd(FunctionalState NewState)
546 {
547 /* Check the parameters */
548
549 assert_param(IS_FUNCTIONAL_STATE(NewState));
550 *(__IO uint32_t *) CR_PLL3ON_BB = (uint32_t)NewState;
\ RCC_PLL3Cmd:
\ 00000000 ........ LDR.W R1,??DataTable39_10 ;; 0x42420070
\ 00000004 C0B2 UXTB R0,R0 ;; ZeroExt R0,R0,#+24,#+24
\ 00000006 0860 STR R0,[R1, #+0]
551 }
\ 00000008 7047 BX LR ;; return
552 #endif /* STM32F10X_CL */
553
554 /**
555 * @brief Configures the system clock (SYSCLK).
556 * @param RCC_SYSCLKSource: specifies the clock source used as system clock.
557 * This parameter can be one of the following values:
558 * @arg RCC_SYSCLKSource_HSI: HSI selected as system clock
559 * @arg RCC_SYSCLKSource_HSE: HSE selected as system clock
560 * @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock
561 * @retval None
562 */
\ In section .text, align 2, keep-with-next
563 void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)
564 {
565 uint32_t tmpreg = 0;
\ RCC_SYSCLKConfig:
\ 00000000 0021 MOVS R1,#+0
566 /* Check the parameters */
567 assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource));
568 tmpreg = RCC->CFGR;
\ 00000002 ........ LDR.W R2,??DataTable39_1 ;; 0x40021004
\ 00000006 1268 LDR R2,[R2, #+0]
\ 00000008 1100 MOVS R1,R2
569 /* Clear SW[1:0] bits */
570 tmpreg &= CFGR_SW_Mask;
\ 0000000A 8908 LSRS R1,R1,#+2
\ 0000000C 8900 LSLS R1,R1,#+2
571 /* Set SW[1:0] bits according to RCC_SYSCLKSource value */
572 tmpreg |= RCC_SYSCLKSource;
\ 0000000E 0143 ORRS R1,R0,R1
573 /* Store the new value */
574 RCC->CFGR = tmpreg;
\ 00000010 ........ LDR.W R2,??DataTable39_1 ;; 0x40021004
\ 00000014 1160 STR R1,[R2, #+0]
575 }
\ 00000016 7047 BX LR ;; return
576
577 /**
578 * @brief Returns the clock source used as system clock.
579 * @param None
580 * @retval The clock source used as system clock. The returned value can
581 * be one of the following:
582 * - 0x00: HSI used as system clock
583 * - 0x04: HSE used as system clock
584 * - 0x08: PLL used as system clock
585 */
\ In section .text, align 2, keep-with-next
586 uint8_t RCC_GetSYSCLKSource(void)
587 {
588 return ((uint8_t)(RCC->CFGR & CFGR_SWS_Mask));
\ RCC_GetSYSCLKSource:
\ 00000000 ........ LDR.W R0,??DataTable39_1 ;; 0x40021004
\ 00000004 0068 LDR R0,[R0, #+0]
\ 00000006 10F00C00 ANDS R0,R0,#0xC
\ 0000000A 7047 BX LR ;; return
589 }
590
591 /**
592 * @brief Configures the AHB clock (HCLK).
593 * @param RCC_SYSCLK: defines the AHB clock divider. This clock is derived from
594 * the system clock (SYSCLK).
595 * This parameter can be one of the following values:
596 * @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK
597 * @arg RCC_SYSCLK_Div2: AHB clock = SYSCLK/2
598 * @arg RCC_SYSCLK_Div4: AHB clock = SYSCLK/4
599 * @arg RCC_SYSCLK_Div8: AHB clock = SYSCLK/8
600 * @arg RCC_SYSCLK_Div16: AHB clock = SYSCLK/16
601 * @arg RCC_SYSCLK_Div64: AHB clock = SYSCLK/64
602 * @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128
603 * @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256
604 * @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512
605 * @retval None
606 */
\ In section .text, align 2, keep-with-next
607 void RCC_HCLKConfig(uint32_t RCC_SYSCLK)
608 {
609 uint32_t tmpreg = 0;
\ RCC_HCLKConfig:
\ 00000000 0021 MOVS R1,#+0
610 /* Check the parameters */
611 assert_param(IS_RCC_HCLK(RCC_SYSCLK));
612 tmpreg = RCC->CFGR;
\ 00000002 ........ LDR.W R2,??DataTable39_1 ;; 0x40021004
\ 00000006 1268 LDR R2,[R2, #+0]
\ 00000008 1100 MOVS R1,R2
613 /* Clear HPRE[3:0] bits */
614 tmpreg &= CFGR_HPRE_Reset_Mask;
\ 0000000A 31F0F001 BICS R1,R1,#0xF0
615 /* Set HPRE[3:0] bits according to RCC_SYSCLK value */
616 tmpreg |= RCC_SYSCLK;
\ 0000000E 0143 ORRS R1,R0,R1
617 /* Store the new value */
618 RCC->CFGR = tmpreg;
\ 00000010 ........ LDR.W R2,??DataTable39_1 ;; 0x40021004
\ 00000014 1160 STR R1,[R2, #+0]
619 }
\ 00000016 7047 BX LR ;; return
620
621 /**
622 * @brief Configures the Low Speed APB clock (PCLK1).
623 * @param RCC_HCLK: defines the APB1 clock divider. This clock is derived from
624 * the AHB clock (HCLK).
625 * This parameter can be one of the following values:
626 * @arg RCC_HCLK_Div1: APB1 clock = HCLK
627 * @arg RCC_HCLK_Div2: APB1 clock = HCLK/2
628 * @arg RCC_HCLK_Div4: APB1 clock = HCLK/4
629 * @arg RCC_HCLK_Div8: APB1 clock = HCLK/8
630 * @arg RCC_HCLK_Div16: APB1 clock = HCLK/16
631 * @retval None
632 */
\ In section .text, align 2, keep-with-next
633 void RCC_PCLK1Config(uint32_t RCC_HCLK)
634 {
635 uint32_t tmpreg = 0;
\ RCC_PCLK1Config:
\ 00000000 0021 MOVS R1,#+0
636 /* Check the parameters */
637 assert_param(IS_RCC_PCLK(RCC_HCLK));
638 tmpreg = RCC->CFGR;
\ 00000002 ........ LDR.W R2,??DataTable39_1 ;; 0x40021004
\ 00000006 1268 LDR R2,[R2, #+0]
\ 00000008 1100 MOVS R1,R2
639 /* Clear PPRE1[2:0] bits */
640 tmpreg &= CFGR_PPRE1_Reset_Mask;
\ 0000000A 31F4E061 BICS R1,R1,#0x700
641 /* Set PPRE1[2:0] bits according to RCC_HCLK value */
642 tmpreg |= RCC_HCLK;
\ 0000000E 0143 ORRS R1,R0,R1
643 /* Store the new value */
644 RCC->CFGR = tmpreg;
\ 00000010 ........ LDR.W R2,??DataTable39_1 ;; 0x40021004
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