📄 stm32f10x_rcc.lst
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\ 00000034 01E0 B.N ??RCC_WaitForHSEStartUp_3
319 }
320 else
321 {
322 status = ERROR;
\ ??RCC_WaitForHSEStartUp_2:
\ 00000036 0020 MOVS R0,#+0
\ 00000038 0400 MOVS R4,R0
323 }
324 return (status);
\ ??RCC_WaitForHSEStartUp_3:
\ 0000003A 2000 MOVS R0,R4
\ 0000003C C0B2 UXTB R0,R0 ;; ZeroExt R0,R0,#+24,#+24
\ 0000003E 32BD POP {R1,R4,R5,PC} ;; return
325 }
326
327 /**
328 * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value.
329 * @param HSICalibrationValue: specifies the calibration trimming value.
330 * This parameter must be a number between 0 and 0x1F.
331 * @retval None
332 */
\ In section .text, align 2, keep-with-next
333 void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue)
334 {
335 uint32_t tmpreg = 0;
\ RCC_AdjustHSICalibrationValue:
\ 00000000 0021 MOVS R1,#+0
336 /* Check the parameters */
337 assert_param(IS_RCC_CALIBRATION_VALUE(HSICalibrationValue));
338 tmpreg = RCC->CR;
\ 00000002 ........ LDR.W R2,??DataTable39 ;; 0x40021000
\ 00000006 1268 LDR R2,[R2, #+0]
\ 00000008 1100 MOVS R1,R2
339 /* Clear HSITRIM[4:0] bits */
340 tmpreg &= CR_HSITRIM_Mask;
\ 0000000A 31F0F801 BICS R1,R1,#0xF8
341 /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */
342 tmpreg |= (uint32_t)HSICalibrationValue << 3;
\ 0000000E C0B2 UXTB R0,R0 ;; ZeroExt R0,R0,#+24,#+24
\ 00000010 51EAC001 ORRS R1,R1,R0, LSL #+3
343 /* Store the new value */
344 RCC->CR = tmpreg;
\ 00000014 ........ LDR.W R2,??DataTable39 ;; 0x40021000
\ 00000018 1160 STR R1,[R2, #+0]
345 }
\ 0000001A 7047 BX LR ;; return
346
347 /**
348 * @brief Enables or disables the Internal High Speed oscillator (HSI).
349 * @note HSI can not be stopped if it is used directly or through the PLL as system clock.
350 * @param NewState: new state of the HSI. This parameter can be: ENABLE or DISABLE.
351 * @retval None
352 */
\ In section .text, align 2, keep-with-next
353 void RCC_HSICmd(FunctionalState NewState)
354 {
355 /* Check the parameters */
356 assert_param(IS_FUNCTIONAL_STATE(NewState));
357 *(__IO uint32_t *) CR_HSION_BB = (uint32_t)NewState;
\ RCC_HSICmd:
\ 00000000 ........ LDR.W R1,??DataTable39_6 ;; 0x42420000
\ 00000004 C0B2 UXTB R0,R0 ;; ZeroExt R0,R0,#+24,#+24
\ 00000006 0860 STR R0,[R1, #+0]
358 }
\ 00000008 7047 BX LR ;; return
359
360 /**
361 * @brief Configures the PLL clock source and multiplication factor.
362 * @note This function must be used only when the PLL is disabled.
363 * @param RCC_PLLSource: specifies the PLL entry clock source.
364 * For @b STM32_Connectivity_line_devices or @b STM32_Value_line_devices,
365 * this parameter can be one of the following values:
366 * @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock divided by 2 selected as PLL clock entry
367 * @arg RCC_PLLSource_PREDIV1: PREDIV1 clock selected as PLL clock entry
368 * For @b other_STM32_devices, this parameter can be one of the following values:
369 * @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock divided by 2 selected as PLL clock entry
370 * @arg RCC_PLLSource_HSE_Div1: HSE oscillator clock selected as PLL clock entry
371 * @arg RCC_PLLSource_HSE_Div2: HSE oscillator clock divided by 2 selected as PLL clock entry
372 * @param RCC_PLLMul: specifies the PLL multiplication factor.
373 * For @b STM32_Connectivity_line_devices, this parameter can be RCC_PLLMul_x where x:{[4,9], 6_5}
374 * For @b other_STM32_devices, this parameter can be RCC_PLLMul_x where x:[2,16]
375 * @retval None
376 */
\ In section .text, align 2, keep-with-next
377 void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul)
378 {
379 uint32_t tmpreg = 0;
\ RCC_PLLConfig:
\ 00000000 0022 MOVS R2,#+0
380
381 /* Check the parameters */
382 assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource));
383 assert_param(IS_RCC_PLL_MUL(RCC_PLLMul));
384
385 tmpreg = RCC->CFGR;
\ 00000002 ........ LDR.W R3,??DataTable39_1 ;; 0x40021004
\ 00000006 1B68 LDR R3,[R3, #+0]
\ 00000008 1A00 MOVS R2,R3
386 /* Clear PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
387 tmpreg &= CFGR_PLL_Mask;
\ 0000000A 32F47412 BICS R2,R2,#0x3D0000
388 /* Set the PLL configuration bits */
389 tmpreg |= RCC_PLLSource | RCC_PLLMul;
\ 0000000E 51EA0003 ORRS R3,R1,R0
\ 00000012 1A43 ORRS R2,R3,R2
390 /* Store the new value */
391 RCC->CFGR = tmpreg;
\ 00000014 ........ LDR.W R3,??DataTable39_1 ;; 0x40021004
\ 00000018 1A60 STR R2,[R3, #+0]
392 }
\ 0000001A 7047 BX LR ;; return
393
394 /**
395 * @brief Enables or disables the PLL.
396 * @note The PLL can not be disabled if it is used as system clock.
397 * @param NewState: new state of the PLL. This parameter can be: ENABLE or DISABLE.
398 * @retval None
399 */
\ In section .text, align 2, keep-with-next
400 void RCC_PLLCmd(FunctionalState NewState)
401 {
402 /* Check the parameters */
403 assert_param(IS_FUNCTIONAL_STATE(NewState));
404
405 *(__IO uint32_t *) CR_PLLON_BB = (uint32_t)NewState;
\ RCC_PLLCmd:
\ 00000000 ........ LDR.W R1,??DataTable39_7 ;; 0x42420060
\ 00000004 C0B2 UXTB R0,R0 ;; ZeroExt R0,R0,#+24,#+24
\ 00000006 0860 STR R0,[R1, #+0]
406 }
\ 00000008 7047 BX LR ;; return
407
408 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL)
409 /**
410 * @brief Configures the PREDIV1 division factor.
411 * @note
412 * - This function must be used only when the PLL is disabled.
413 * - This function applies only to STM32 Connectivity line and Value line
414 * devices.
415 * @param RCC_PREDIV1_Source: specifies the PREDIV1 clock source.
416 * This parameter can be one of the following values:
417 * @arg RCC_PREDIV1_Source_HSE: HSE selected as PREDIV1 clock
418 * @arg RCC_PREDIV1_Source_PLL2: PLL2 selected as PREDIV1 clock
419 * @note
420 * For @b STM32_Value_line_devices this parameter is always RCC_PREDIV1_Source_HSE
421 * @param RCC_PREDIV1_Div: specifies the PREDIV1 clock division factor.
422 * This parameter can be RCC_PREDIV1_Divx where x:[1,16]
423 * @retval None
424 */
\ In section .text, align 2, keep-with-next
425 void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Source, uint32_t RCC_PREDIV1_Div)
426 {
427 uint32_t tmpreg = 0;
\ RCC_PREDIV1Config:
\ 00000000 0022 MOVS R2,#+0
428
429 /* Check the parameters */
430 assert_param(IS_RCC_PREDIV1_SOURCE(RCC_PREDIV1_Source));
431 assert_param(IS_RCC_PREDIV1(RCC_PREDIV1_Div));
432
433 tmpreg = RCC->CFGR2;
\ 00000002 ........ LDR.W R3,??DataTable39_5 ;; 0x4002102c
\ 00000006 1B68 LDR R3,[R3, #+0]
\ 00000008 1A00 MOVS R2,R3
434 /* Clear PREDIV1[3:0] and PREDIV1SRC bits */
435 tmpreg &= ~(CFGR2_PREDIV1 | CFGR2_PREDIV1SRC);
\ 0000000A ........ LDR.W R3,??DataTable39_8 ;; 0xfffefff0
\ 0000000E 1A40 ANDS R2,R3,R2
436 /* Set the PREDIV1 clock source and division factor */
437 tmpreg |= RCC_PREDIV1_Source | RCC_PREDIV1_Div ;
\ 00000010 51EA0003 ORRS R3,R1,R0
\ 00000014 1A43 ORRS R2,R3,R2
438 /* Store the new value */
439 RCC->CFGR2 = tmpreg;
\ 00000016 ........ LDR.W R3,??DataTable39_5 ;; 0x4002102c
\ 0000001A 1A60 STR R2,[R3, #+0]
440 }
\ 0000001C 7047 BX LR ;; return
441 #endif
442
443 #ifdef STM32F10X_CL
444 /**
445 * @brief Configures the PREDIV2 division factor.
446 * @note
447 * - This function must be used only when both PLL2 and PLL3 are disabled.
448 * - This function applies only to STM32 Connectivity line devices.
449 * @param RCC_PREDIV2_Div: specifies the PREDIV2 clock division factor.
450 * This parameter can be RCC_PREDIV2_Divx where x:[1,16]
451 * @retval None
452 */
\ In section .text, align 2, keep-with-next
453 void RCC_PREDIV2Config(uint32_t RCC_PREDIV2_Div)
454 {
455 uint32_t tmpreg = 0;
\ RCC_PREDIV2Config:
\ 00000000 0021 MOVS R1,#+0
456
457 /* Check the parameters */
458 assert_param(IS_RCC_PREDIV2(RCC_PREDIV2_Div));
459
460 tmpreg = RCC->CFGR2;
\ 00000002 ........ LDR.W R2,??DataTable39_5 ;; 0x4002102c
\ 00000006 1268 LDR R2,[R2, #+0]
\ 00000008 1100 MOVS R1,R2
461 /* Clear PREDIV2[3:0] bits */
462 tmpreg &= ~CFGR2_PREDIV2;
\ 0000000A 31F0F001 BICS R1,R1,#0xF0
463 /* Set the PREDIV2 division factor */
464 tmpreg |= RCC_PREDIV2_Div;
\ 0000000E 0143 ORRS R1,R0,R1
465 /* Store the new value */
466 RCC->CFGR2 = tmpreg;
\ 00000010 ........ LDR.W R2,??DataTable39_5 ;; 0x4002102c
\ 00000014 1160 STR R1,[R2, #+0]
467 }
\ 00000016 7047 BX LR ;; return
468
469 /**
470 * @brief Configures the PLL2 multiplication factor.
471 * @note
472 * - This function must be used only when the PLL2 is disabled.
473 * - This function applies only to STM32 Connectivity line devices.
474 * @param RCC_PLL2Mul: specifies the PLL2 multiplication factor.
475 * This parameter can be RCC_PLL2Mul_x where x:{[8,14], 16, 20}
476 * @retval None
477 */
\ In section .text, align 2, keep-with-next
478 void RCC_PLL2Config(uint32_t RCC_PLL2Mul)
479 {
480 uint32_t tmpreg = 0;
\ RCC_PLL2Config:
\ 00000000 0021 MOVS R1,#+0
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