📄 stm32f10x_rcc.lst
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\ APBAHBPrescTable:
\ 00000000 000000000102 DC8 0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9
\ 030401020304
\ 06070809
\ In section .data, align 4
193 static __I uint8_t ADCPrescTable[4] = {2, 4, 6, 8};
\ ADCPrescTable:
\ 00000000 02040608 DC8 2, 4, 6, 8
194
195 /**
196 * @}
197 */
198
199 /** @defgroup RCC_Private_FunctionPrototypes
200 * @{
201 */
202
203 /**
204 * @}
205 */
206
207 /** @defgroup RCC_Private_Functions
208 * @{
209 */
210
211 /**
212 * @brief Resets the RCC clock configuration to the default reset state.
213 * @param None
214 * @retval None
215 */
\ In section .text, align 2, keep-with-next
216 void RCC_DeInit(void)
217 {
218 /* Set HSION bit */
219 RCC->CR |= (uint32_t)0x00000001;
\ RCC_DeInit:
\ 00000000 ........ LDR.W R0,??DataTable39 ;; 0x40021000
\ 00000004 0068 LDR R0,[R0, #+0]
\ 00000006 50F00100 ORRS R0,R0,#0x1
\ 0000000A ........ LDR.W R1,??DataTable39 ;; 0x40021000
\ 0000000E 0860 STR R0,[R1, #+0]
220
221 /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
222 #ifndef STM32F10X_CL
223 RCC->CFGR &= (uint32_t)0xF8FF0000;
224 #else
225 RCC->CFGR &= (uint32_t)0xF0FF0000;
\ 00000010 ........ LDR.W R0,??DataTable39_1 ;; 0x40021004
\ 00000014 0068 LDR R0,[R0, #+0]
\ 00000016 ........ LDR.W R1,??DataTable39_2 ;; 0xf0ff0000
\ 0000001A 0840 ANDS R0,R1,R0
\ 0000001C ........ LDR.W R1,??DataTable39_1 ;; 0x40021004
\ 00000020 0860 STR R0,[R1, #+0]
226 #endif /* STM32F10X_CL */
227
228 /* Reset HSEON, CSSON and PLLON bits */
229 RCC->CR &= (uint32_t)0xFEF6FFFF;
\ 00000022 ........ LDR.W R0,??DataTable39 ;; 0x40021000
\ 00000026 0068 LDR R0,[R0, #+0]
\ 00000028 ........ LDR.W R1,??DataTable39_3 ;; 0xfef6ffff
\ 0000002C 0840 ANDS R0,R1,R0
\ 0000002E ........ LDR.W R1,??DataTable39 ;; 0x40021000
\ 00000032 0860 STR R0,[R1, #+0]
230
231 /* Reset HSEBYP bit */
232 RCC->CR &= (uint32_t)0xFFFBFFFF;
\ 00000034 ........ LDR.W R0,??DataTable39 ;; 0x40021000
\ 00000038 0068 LDR R0,[R0, #+0]
\ 0000003A 30F48020 BICS R0,R0,#0x40000
\ 0000003E ........ LDR.W R1,??DataTable39 ;; 0x40021000
\ 00000042 0860 STR R0,[R1, #+0]
233
234 /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
235 RCC->CFGR &= (uint32_t)0xFF80FFFF;
\ 00000044 ........ LDR.W R0,??DataTable39_1 ;; 0x40021004
\ 00000048 0068 LDR R0,[R0, #+0]
\ 0000004A 30F4FE00 BICS R0,R0,#0x7F0000
\ 0000004E ........ LDR.W R1,??DataTable39_1 ;; 0x40021004
\ 00000052 0860 STR R0,[R1, #+0]
236
237 #ifdef STM32F10X_CL
238 /* Reset PLL2ON and PLL3ON bits */
239 RCC->CR &= (uint32_t)0xEBFFFFFF;
\ 00000054 ........ LDR.W R0,??DataTable39 ;; 0x40021000
\ 00000058 0068 LDR R0,[R0, #+0]
\ 0000005A 30F0A050 BICS R0,R0,#0x14000000
\ 0000005E ........ LDR.W R1,??DataTable39 ;; 0x40021000
\ 00000062 0860 STR R0,[R1, #+0]
240
241 /* Disable all interrupts and clear pending bits */
242 RCC->CIR = 0x00FF0000;
\ 00000064 ........ LDR.W R0,??DataTable39_4 ;; 0x40021008
\ 00000068 5FF47F01 MOVS R1,#+16711680
\ 0000006C 0160 STR R1,[R0, #+0]
243
244 /* Reset CFGR2 register */
245 RCC->CFGR2 = 0x00000000;
\ 0000006E ........ LDR.W R0,??DataTable39_5 ;; 0x4002102c
\ 00000072 0021 MOVS R1,#+0
\ 00000074 0160 STR R1,[R0, #+0]
246 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
247 /* Disable all interrupts and clear pending bits */
248 RCC->CIR = 0x009F0000;
249
250 /* Reset CFGR2 register */
251 RCC->CFGR2 = 0x00000000;
252 #else
253 /* Disable all interrupts and clear pending bits */
254 RCC->CIR = 0x009F0000;
255 #endif /* STM32F10X_CL */
256
257 }
\ 00000076 7047 BX LR ;; return
258
259 /**
260 * @brief Configures the External High Speed oscillator (HSE).
261 * @note HSE can not be stopped if it is used directly or through the PLL as system clock.
262 * @param RCC_HSE: specifies the new state of the HSE.
263 * This parameter can be one of the following values:
264 * @arg RCC_HSE_OFF: HSE oscillator OFF
265 * @arg RCC_HSE_ON: HSE oscillator ON
266 * @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock
267 * @retval None
268 */
\ In section .text, align 2, keep-with-next
269 void RCC_HSEConfig(uint32_t RCC_HSE)
270 {
271 /* Check the parameters */
272 assert_param(IS_RCC_HSE(RCC_HSE));
273 /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/
274 /* Reset HSEON bit */
275 RCC->CR &= CR_HSEON_Reset;
\ RCC_HSEConfig:
\ 00000000 ........ LDR.W R1,??DataTable39 ;; 0x40021000
\ 00000004 0968 LDR R1,[R1, #+0]
\ 00000006 31F48031 BICS R1,R1,#0x10000
\ 0000000A ........ LDR.W R2,??DataTable39 ;; 0x40021000
\ 0000000E 1160 STR R1,[R2, #+0]
276 /* Reset HSEBYP bit */
277 RCC->CR &= CR_HSEBYP_Reset;
\ 00000010 ........ LDR.W R1,??DataTable39 ;; 0x40021000
\ 00000014 0968 LDR R1,[R1, #+0]
\ 00000016 31F48021 BICS R1,R1,#0x40000
\ 0000001A ........ LDR.W R2,??DataTable39 ;; 0x40021000
\ 0000001E 1160 STR R1,[R2, #+0]
278 /* Configure HSE (RCC_HSE_OFF is already covered by the code section above) */
279 switch(RCC_HSE)
\ 00000020 0100 MOVS R1,R0
\ 00000022 B1F5803F CMP R1,#+65536
\ 00000026 03D0 BEQ.N ??RCC_HSEConfig_0
\ 00000028 B1F5802F CMP R1,#+262144
\ 0000002C 09D0 BEQ.N ??RCC_HSEConfig_1
\ 0000002E 11E0 B.N ??RCC_HSEConfig_2
280 {
281 case RCC_HSE_ON:
282 /* Set HSEON bit */
283 RCC->CR |= CR_HSEON_Set;
\ ??RCC_HSEConfig_0:
\ 00000030 ........ LDR.W R1,??DataTable39 ;; 0x40021000
\ 00000034 0968 LDR R1,[R1, #+0]
\ 00000036 51F48031 ORRS R1,R1,#0x10000
\ 0000003A ........ LDR.W R2,??DataTable39 ;; 0x40021000
\ 0000003E 1160 STR R1,[R2, #+0]
284 break;
\ 00000040 08E0 B.N ??RCC_HSEConfig_3
285
286 case RCC_HSE_Bypass:
287 /* Set HSEBYP and HSEON bits */
288 RCC->CR |= CR_HSEBYP_Set | CR_HSEON_Set;
\ ??RCC_HSEConfig_1:
\ 00000042 ........ LDR.W R1,??DataTable39 ;; 0x40021000
\ 00000046 0968 LDR R1,[R1, #+0]
\ 00000048 51F4A021 ORRS R1,R1,#0x50000
\ 0000004C ........ LDR.W R2,??DataTable39 ;; 0x40021000
\ 00000050 1160 STR R1,[R2, #+0]
289 break;
\ 00000052 FFE7 B.N ??RCC_HSEConfig_3
290
291 default:
292 break;
293 }
294 }
\ ??RCC_HSEConfig_2:
\ ??RCC_HSEConfig_3:
\ 00000054 7047 BX LR ;; return
295
296 /**
297 * @brief Waits for HSE start-up.
298 * @param None
299 * @retval An ErrorStatus enumuration value:
300 * - SUCCESS: HSE oscillator is stable and ready to use
301 * - ERROR: HSE oscillator not yet ready
302 */
\ In section .text, align 2, keep-with-next
303 ErrorStatus RCC_WaitForHSEStartUp(void)
304 {
\ RCC_WaitForHSEStartUp:
\ 00000000 38B5 PUSH {R3-R5,LR}
305 __IO uint32_t StartUpCounter = 0;
\ 00000002 0020 MOVS R0,#+0
\ 00000004 0090 STR R0,[SP, #+0]
306 ErrorStatus status = ERROR;
\ 00000006 0024 MOVS R4,#+0
307 FlagStatus HSEStatus = RESET;
\ 00000008 0025 MOVS R5,#+0
308
309 /* Wait till HSE is ready and if Time out is reached exit */
310 do
311 {
312 HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY);
\ ??RCC_WaitForHSEStartUp_0:
\ 0000000A 3120 MOVS R0,#+49
\ 0000000C ........ BL RCC_GetFlagStatus
\ 00000010 0500 MOVS R5,R0
313 StartUpCounter++;
\ 00000012 0098 LDR R0,[SP, #+0]
\ 00000014 401C ADDS R0,R0,#+1
\ 00000016 0090 STR R0,[SP, #+0]
314 } while((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET));
\ 00000018 0098 LDR R0,[SP, #+0]
\ 0000001A B0F5A06F CMP R0,#+1280
\ 0000001E 02D0 BEQ.N ??RCC_WaitForHSEStartUp_1
\ 00000020 EDB2 UXTB R5,R5 ;; ZeroExt R5,R5,#+24,#+24
\ 00000022 002D CMP R5,#+0
\ 00000024 F1D0 BEQ.N ??RCC_WaitForHSEStartUp_0
315
316 if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET)
\ ??RCC_WaitForHSEStartUp_1:
\ 00000026 3120 MOVS R0,#+49
\ 00000028 ........ BL RCC_GetFlagStatus
\ 0000002C 0028 CMP R0,#+0
\ 0000002E 02D0 BEQ.N ??RCC_WaitForHSEStartUp_2
317 {
318 status = SUCCESS;
\ 00000030 0120 MOVS R0,#+1
\ 00000032 0400 MOVS R4,R0
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