📄 stm32f10x_rcc.lst
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###############################################################################
# #
# IAR ANSI C/C++ Compiler V6.10.2.52244/W32 for ARM 07/Aug/2011 12:10:38 #
# Copyright 1999-2010 IAR Systems AB. #
# #
# Cpu mode = thumb #
# Endian = little #
# Source file = F:\stm32\我的程序\Micrium\Software\EWARM\BSP\ST\STM32F10 #
# x_StdPeriph_Driver\src\stm32f10x_rcc.c #
# Command line = F:\stm32\我的程序\Micrium\Software\EWARM\BSP\ST\STM32F10 #
# x_StdPeriph_Driver\src\stm32f10x_rcc.c -D #
# USE_STDPERIPH_DRIVER -D STM32F10X_CL -lCN #
# F:\stm32\我的程序\Micrium\Software\EWARM\OS-II\Flash\Lis #
# t\ -o F:\stm32\我的程序\Micrium\Software\EWARM\OS-II\Fla #
# sh\Obj\ --no_cse --no_unroll --no_inline #
# --no_code_motion --no_tbaa --no_clustering #
# --no_scheduling --debug --endian=little --cpu=Cortex-M3 #
# -e --fpu=None --dlib_config #
# D:\arm\INC\c\DLib_Config_Normal.h -I #
# F:\stm32\我的程序\Micrium\Software\EWARM\OS-II\APP\ -I #
# F:\stm32\我的程序\Micrium\Software\EWARM\OS-II\..\BSP\ #
# -I F:\stm32\我的程序\Micrium\Software\EWARM\OS-II\..\BSP #
# \ST\CMSIS\CM3\CoreSupport\ -I #
# F:\stm32\我的程序\Micrium\Software\EWARM\OS-II\..\BSP\ST #
# \CMSIS\CM3\DeviceSupport\ST\STM32F10x\ -I #
# F:\stm32\我的程序\Micrium\Software\EWARM\OS-II\..\BSP\ST #
# \STM32F10x_StdPeriph_Driver\inc\ -I #
# F:\stm32\我的程序\Micrium\Software\EWARM\OS-II\..\BSP\uC #
# OS-II\ -I F:\stm32\我的程序\Micrium\Software\EWARM\OS-II #
# \..\..\uCOS-II\Ports\ARM-Cortex-M3\Generic\IAR\ -I #
# F:\stm32\我的程序\Micrium\Software\EWARM\OS-II\..\..\uCO #
# S-II\Source\ -I F:\stm32\我的程序\Micrium\Software\EWARM #
# \OS-II\..\..\uC-LIB\ -I F:\stm32\我的程序\Micrium\Softwa #
# re\EWARM\OS-II\..\..\uC-LIB\Ports\ARM-Cortex-M3\IAR\ -I #
# F:\stm32\我的程序\Micrium\Software\EWARM\OS-II\..\..\uC- #
# CPU\ -I F:\stm32\我的程序\Micrium\Software\EWARM\OS-II\. #
# .\..\uC-CPU\ARM-Cortex-M3\IAR\ -On --use_c++_inline #
# List file = F:\stm32\我的程序\Micrium\Software\EWARM\OS-II\Flash\Lis #
# t\stm32f10x_rcc.lst #
# Object file = F:\stm32\我的程序\Micrium\Software\EWARM\OS-II\Flash\Obj #
# \stm32f10x_rcc.o #
# #
# #
###############################################################################
F:\stm32\我的程序\Micrium\Software\EWARM\BSP\ST\STM32F10x_StdPeriph_Driver\src\stm32f10x_rcc.c
1 /**
2 ******************************************************************************
3 * @file stm32f10x_rcc.c
4 * @author MCD Application Team
5 * @version V3.4.0
6 * @date 10/15/2010
7 * @brief This file provides all the RCC firmware functions.
8 ******************************************************************************
9 * @copy
10 *
11 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
12 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
13 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
14 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
15 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
16 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
17 *
18 * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
19 */
20
21 /* Includes ------------------------------------------------------------------*/
22 #include "stm32f10x_rcc.h"
23
24 /** @addtogroup STM32F10x_StdPeriph_Driver
25 * @{
26 */
27
28 /** @defgroup RCC
29 * @brief RCC driver modules
30 * @{
31 */
32
33 /** @defgroup RCC_Private_TypesDefinitions
34 * @{
35 */
36
37 /**
38 * @}
39 */
40
41 /** @defgroup RCC_Private_Defines
42 * @{
43 */
44
45 /* ------------ RCC registers bit address in the alias region ----------- */
46 #define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
47
48 /* --- CR Register ---*/
49
50 /* Alias word address of HSION bit */
51 #define CR_OFFSET (RCC_OFFSET + 0x00)
52 #define HSION_BitNumber 0x00
53 #define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4))
54
55 /* Alias word address of PLLON bit */
56 #define PLLON_BitNumber 0x18
57 #define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4))
58
59 #ifdef STM32F10X_CL
60 /* Alias word address of PLL2ON bit */
61 #define PLL2ON_BitNumber 0x1A
62 #define CR_PLL2ON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLL2ON_BitNumber * 4))
63
64 /* Alias word address of PLL3ON bit */
65 #define PLL3ON_BitNumber 0x1C
66 #define CR_PLL3ON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLL3ON_BitNumber * 4))
67 #endif /* STM32F10X_CL */
68
69 /* Alias word address of CSSON bit */
70 #define CSSON_BitNumber 0x13
71 #define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4))
72
73 /* --- CFGR Register ---*/
74
75 /* Alias word address of USBPRE bit */
76 #define CFGR_OFFSET (RCC_OFFSET + 0x04)
77
78 #ifndef STM32F10X_CL
79 #define USBPRE_BitNumber 0x16
80 #define CFGR_USBPRE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (USBPRE_BitNumber * 4))
81 #else
82 #define OTGFSPRE_BitNumber 0x16
83 #define CFGR_OTGFSPRE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (OTGFSPRE_BitNumber * 4))
84 #endif /* STM32F10X_CL */
85
86 /* --- BDCR Register ---*/
87
88 /* Alias word address of RTCEN bit */
89 #define BDCR_OFFSET (RCC_OFFSET + 0x20)
90 #define RTCEN_BitNumber 0x0F
91 #define BDCR_RTCEN_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4))
92
93 /* Alias word address of BDRST bit */
94 #define BDRST_BitNumber 0x10
95 #define BDCR_BDRST_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4))
96
97 /* --- CSR Register ---*/
98
99 /* Alias word address of LSION bit */
100 #define CSR_OFFSET (RCC_OFFSET + 0x24)
101 #define LSION_BitNumber 0x00
102 #define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4))
103
104 #ifdef STM32F10X_CL
105 /* --- CFGR2 Register ---*/
106
107 /* Alias word address of I2S2SRC bit */
108 #define CFGR2_OFFSET (RCC_OFFSET + 0x2C)
109 #define I2S2SRC_BitNumber 0x11
110 #define CFGR2_I2S2SRC_BB (PERIPH_BB_BASE + (CFGR2_OFFSET * 32) + (I2S2SRC_BitNumber * 4))
111
112 /* Alias word address of I2S3SRC bit */
113 #define I2S3SRC_BitNumber 0x12
114 #define CFGR2_I2S3SRC_BB (PERIPH_BB_BASE + (CFGR2_OFFSET * 32) + (I2S3SRC_BitNumber * 4))
115 #endif /* STM32F10X_CL */
116
117 /* ---------------------- RCC registers bit mask ------------------------ */
118
119 /* CR register bit mask */
120 #define CR_HSEBYP_Reset ((uint32_t)0xFFFBFFFF)
121 #define CR_HSEBYP_Set ((uint32_t)0x00040000)
122 #define CR_HSEON_Reset ((uint32_t)0xFFFEFFFF)
123 #define CR_HSEON_Set ((uint32_t)0x00010000)
124 #define CR_HSITRIM_Mask ((uint32_t)0xFFFFFF07)
125
126 /* CFGR register bit mask */
127 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL)
128 #define CFGR_PLL_Mask ((uint32_t)0xFFC2FFFF)
129 #else
130 #define CFGR_PLL_Mask ((uint32_t)0xFFC0FFFF)
131 #endif /* STM32F10X_CL */
132
133 #define CFGR_PLLMull_Mask ((uint32_t)0x003C0000)
134 #define CFGR_PLLSRC_Mask ((uint32_t)0x00010000)
135 #define CFGR_PLLXTPRE_Mask ((uint32_t)0x00020000)
136 #define CFGR_SWS_Mask ((uint32_t)0x0000000C)
137 #define CFGR_SW_Mask ((uint32_t)0xFFFFFFFC)
138 #define CFGR_HPRE_Reset_Mask ((uint32_t)0xFFFFFF0F)
139 #define CFGR_HPRE_Set_Mask ((uint32_t)0x000000F0)
140 #define CFGR_PPRE1_Reset_Mask ((uint32_t)0xFFFFF8FF)
141 #define CFGR_PPRE1_Set_Mask ((uint32_t)0x00000700)
142 #define CFGR_PPRE2_Reset_Mask ((uint32_t)0xFFFFC7FF)
143 #define CFGR_PPRE2_Set_Mask ((uint32_t)0x00003800)
144 #define CFGR_ADCPRE_Reset_Mask ((uint32_t)0xFFFF3FFF)
145 #define CFGR_ADCPRE_Set_Mask ((uint32_t)0x0000C000)
146
147 /* CSR register bit mask */
148 #define CSR_RMVF_Set ((uint32_t)0x01000000)
149
150 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL)
151 /* CFGR2 register bit mask */
152 #define CFGR2_PREDIV1SRC ((uint32_t)0x00010000)
153 #define CFGR2_PREDIV1 ((uint32_t)0x0000000F)
154 #endif
155 #ifdef STM32F10X_CL
156 #define CFGR2_PREDIV2 ((uint32_t)0x000000F0)
157 #define CFGR2_PLL2MUL ((uint32_t)0x00000F00)
158 #define CFGR2_PLL3MUL ((uint32_t)0x0000F000)
159 #endif /* STM32F10X_CL */
160
161 /* RCC Flag Mask */
162 #define FLAG_Mask ((uint8_t)0x1F)
163
164 /* CIR register byte 2 (Bits[15:8]) base address */
165 #define CIR_BYTE2_ADDRESS ((uint32_t)0x40021009)
166
167 /* CIR register byte 3 (Bits[23:16]) base address */
168 #define CIR_BYTE3_ADDRESS ((uint32_t)0x4002100A)
169
170 /* CFGR register byte 4 (Bits[31:24]) base address */
171 #define CFGR_BYTE4_ADDRESS ((uint32_t)0x40021007)
172
173 /* BDCR register base address */
174 #define BDCR_ADDRESS (PERIPH_BASE + BDCR_OFFSET)
175
176 /**
177 * @}
178 */
179
180 /** @defgroup RCC_Private_Macros
181 * @{
182 */
183
184 /**
185 * @}
186 */
187
188 /** @defgroup RCC_Private_Variables
189 * @{
190 */
191
\ In section .data, align 4
192 static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
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