📄 stm32f10x_dma.lst
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554 * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
555 * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.
556 * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
557 * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
558 * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
559 * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.
560 * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
561 * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
562 * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
563 * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt.
564 * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.
565 * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.
566 * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.
567 * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt.
568 * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.
569 * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.
570 * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.
571 * @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt.
572 * @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt.
573 * @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt.
574 * @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt.
575 * @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt.
576 * @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt.
577 * @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt.
578 * @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt.
579 * @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt.
580 * @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt.
581 * @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt.
582 * @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt.
583 * @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt.
584 * @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt.
585 * @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt.
586 * @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt.
587 * @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt.
588 * @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt.
589 * @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt.
590 * @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt.
591 * @retval The new state of DMA_IT (SET or RESET).
592 */
\ In section .text, align 2, keep-with-next
593 ITStatus DMA_GetITStatus(uint32_t DMA_IT)
594 {
\ DMA_GetITStatus:
\ 00000000 0100 MOVS R1,R0
595 ITStatus bitstatus = RESET;
\ 00000002 0020 MOVS R0,#+0
596 uint32_t tmpreg = 0;
\ 00000004 0022 MOVS R2,#+0
597 /* Check the parameters */
598 assert_param(IS_DMA_GET_IT(DMA_IT));
599
600 /* Calculate the used DMA */
601 if ((DMA_IT & FLAG_Mask) != (uint32_t)RESET)
\ 00000006 CB00 LSLS R3,R1,#+3
\ 00000008 03D5 BPL.N ??DMA_GetITStatus_0
602 {
603 /* Get DMA2 ISR register value */
604 tmpreg = DMA2->ISR ;
\ 0000000A .... LDR.N R3,??DataTable5_15 ;; 0x40020400
\ 0000000C 1B68 LDR R3,[R3, #+0]
\ 0000000E 1A00 MOVS R2,R3
\ 00000010 02E0 B.N ??DMA_GetITStatus_1
605 }
606 else
607 {
608 /* Get DMA1 ISR register value */
609 tmpreg = DMA1->ISR ;
\ ??DMA_GetITStatus_0:
\ 00000012 .... LDR.N R3,??DataTable5_16 ;; 0x40020000
\ 00000014 1B68 LDR R3,[R3, #+0]
\ 00000016 1A00 MOVS R2,R3
610 }
611
612 /* Check the status of the specified DMA interrupt */
613 if ((tmpreg & DMA_IT) != (uint32_t)RESET)
\ ??DMA_GetITStatus_1:
\ 00000018 0A42 TST R2,R1
\ 0000001A 02D0 BEQ.N ??DMA_GetITStatus_2
614 {
615 /* DMA_IT is set */
616 bitstatus = SET;
\ 0000001C 0123 MOVS R3,#+1
\ 0000001E 1800 MOVS R0,R3
\ 00000020 01E0 B.N ??DMA_GetITStatus_3
617 }
618 else
619 {
620 /* DMA_IT is reset */
621 bitstatus = RESET;
\ ??DMA_GetITStatus_2:
\ 00000022 0023 MOVS R3,#+0
\ 00000024 1800 MOVS R0,R3
622 }
623 /* Return the DMA_IT status */
624 return bitstatus;
\ ??DMA_GetITStatus_3:
\ 00000026 C0B2 UXTB R0,R0 ;; ZeroExt R0,R0,#+24,#+24
\ 00000028 7047 BX LR ;; return
625 }
626
627 /**
628 * @brief Clears the DMAy Channelx抯 interrupt pending bits.
629 * @param DMA_IT: specifies the DMA interrupt pending bit to clear.
630 * This parameter can be any combination (for the same DMA) of the following values:
631 * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.
632 * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
633 * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
634 * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
635 * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.
636 * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
637 * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
638 * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
639 * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.
640 * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
641 * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
642 * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
643 * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.
644 * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
645 * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
646 * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
647 * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.
648 * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
649 * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
650 * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
651 * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt.
652 * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.
653 * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.
654 * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.
655 * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt.
656 * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.
657 * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.
658 * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.
659 * @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt.
660 * @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt.
661 * @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt.
662 * @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt.
663 * @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt.
664 * @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt.
665 * @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt.
666 * @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt.
667 * @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt.
668 * @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt.
669 * @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt.
670 * @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt.
671 * @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt.
672 * @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt.
673 * @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt.
674 * @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt.
675 * @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt.
676 * @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt.
677 * @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt.
678 * @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt.
679 * @retval None
680 */
\ In section .text, align 2, keep-with-next
681 void DMA_ClearITPendingBit(uint32_t DMA_IT)
682 {
683 /* Check the parameters */
684 assert_param(IS_DMA_CLEAR_IT(DMA_IT));
685
686 /* Calculate the used DMA */
687 if ((DMA_IT & FLAG_Mask) != (uint32_t)RESET)
\ DMA_ClearITPendingBit:
\ 00000000 C100 LSLS R1,R0,#+3
\ 00000002 02D5 BPL.N ??DMA_ClearITPendingBit_0
688 {
689 /* Clear the selected DMA interrupt pending bits */
690 DMA2->IFCR = DMA_IT;
\ 00000004 .... LDR.N R1,??DataTable5_9 ;; 0x40020404
\ 00000006 0860 STR R0,[R1, #+0]
\ 00000008 01E0 B.N ??DMA_ClearITPendingBit_1
691 }
692 else
693 {
694 /* Clear the selected DMA interrupt pending bits */
695 DMA1->IFCR = DMA_IT;
\ ??DMA_ClearITPendingBit_0:
\ 0000000A .... LDR.N R1,??DataTable5_1 ;; 0x40020004
\ 0000000C 0860 STR R0,[R1, #+0]
696 }
697 }
\ ??DMA_ClearITPendingBit_1:
\ 0000000E 7047 BX LR ;; return
\ In section .text, align 4, keep-with-next
\ ??DataTable5:
\ 00000000 08000240 DC32 0x40020008
\ In section .text, align 4, keep-with-next
\ ??DataTable5_1:
\ 00000000 04000240 DC32 0x40020004
\ In section .text, align 4, keep-with-next
\ ??DataTable5_2:
\ 00000000 1C000240 DC32 0x4002001c
\ In section .text, align 4, keep-with-next
\ ??DataTable5_3:
\ 00000000 30000240 DC32 0x40020030
\ In section .text, align 4, keep-with-next
\ ??DataTable5_4:
\ 00000000 44000240 DC32 0x40020044
\ In section .text, align 4, keep-with-next
\ ??DataTable5_5:
\ 00000000 58000240 DC32 0x40020058
\ In section .text, align 4, keep-with-next
\ ??DataTable5_6:
\ 00000000 6C000240 DC32 0x4002006c
\ In section .text, align 4, keep-with-next
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