📄 stm32f10x_dma.lst
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\ 00000004 7047 BX LR ;; return
376 }
377
378 /**
379 * @brief Checks whether the specified DMAy Channelx flag is set or not.
380 * @param DMA_FLAG: specifies the flag to check.
381 * This parameter can be one of the following values:
382 * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.
383 * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
384 * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
385 * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
386 * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.
387 * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
388 * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
389 * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
390 * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.
391 * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
392 * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
393 * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
394 * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.
395 * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
396 * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
397 * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
398 * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.
399 * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
400 * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
401 * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
402 * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag.
403 * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
404 * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
405 * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.
406 * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag.
407 * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
408 * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
409 * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.
410 * @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag.
411 * @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.
412 * @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.
413 * @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag.
414 * @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag.
415 * @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.
416 * @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.
417 * @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag.
418 * @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag.
419 * @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.
420 * @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.
421 * @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag.
422 * @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag.
423 * @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.
424 * @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.
425 * @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag.
426 * @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag.
427 * @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.
428 * @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.
429 * @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag.
430 * @retval The new state of DMA_FLAG (SET or RESET).
431 */
\ In section .text, align 2, keep-with-next
432 FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG)
433 {
\ DMA_GetFlagStatus:
\ 00000000 0100 MOVS R1,R0
434 FlagStatus bitstatus = RESET;
\ 00000002 0020 MOVS R0,#+0
435 uint32_t tmpreg = 0;
\ 00000004 0022 MOVS R2,#+0
436 /* Check the parameters */
437 assert_param(IS_DMA_GET_FLAG(DMA_FLAG));
438
439 /* Calculate the used DMA */
440 if ((DMA_FLAG & FLAG_Mask) != (uint32_t)RESET)
\ 00000006 CB00 LSLS R3,R1,#+3
\ 00000008 03D5 BPL.N ??DMA_GetFlagStatus_0
441 {
442 /* Get DMA2 ISR register value */
443 tmpreg = DMA2->ISR ;
\ 0000000A .... LDR.N R3,??DataTable5_15 ;; 0x40020400
\ 0000000C 1B68 LDR R3,[R3, #+0]
\ 0000000E 1A00 MOVS R2,R3
\ 00000010 02E0 B.N ??DMA_GetFlagStatus_1
444 }
445 else
446 {
447 /* Get DMA1 ISR register value */
448 tmpreg = DMA1->ISR ;
\ ??DMA_GetFlagStatus_0:
\ 00000012 .... LDR.N R3,??DataTable5_16 ;; 0x40020000
\ 00000014 1B68 LDR R3,[R3, #+0]
\ 00000016 1A00 MOVS R2,R3
449 }
450
451 /* Check the status of the specified DMA flag */
452 if ((tmpreg & DMA_FLAG) != (uint32_t)RESET)
\ ??DMA_GetFlagStatus_1:
\ 00000018 0A42 TST R2,R1
\ 0000001A 02D0 BEQ.N ??DMA_GetFlagStatus_2
453 {
454 /* DMA_FLAG is set */
455 bitstatus = SET;
\ 0000001C 0123 MOVS R3,#+1
\ 0000001E 1800 MOVS R0,R3
\ 00000020 01E0 B.N ??DMA_GetFlagStatus_3
456 }
457 else
458 {
459 /* DMA_FLAG is reset */
460 bitstatus = RESET;
\ ??DMA_GetFlagStatus_2:
\ 00000022 0023 MOVS R3,#+0
\ 00000024 1800 MOVS R0,R3
461 }
462
463 /* Return the DMA_FLAG status */
464 return bitstatus;
\ ??DMA_GetFlagStatus_3:
\ 00000026 C0B2 UXTB R0,R0 ;; ZeroExt R0,R0,#+24,#+24
\ 00000028 7047 BX LR ;; return
465 }
466
467 /**
468 * @brief Clears the DMAy Channelx's pending flags.
469 * @param DMA_FLAG: specifies the flag to clear.
470 * This parameter can be any combination (for the same DMA) of the following values:
471 * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.
472 * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
473 * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
474 * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
475 * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.
476 * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
477 * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
478 * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
479 * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.
480 * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
481 * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
482 * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
483 * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.
484 * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
485 * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
486 * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
487 * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.
488 * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
489 * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
490 * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
491 * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag.
492 * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
493 * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
494 * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.
495 * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag.
496 * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
497 * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
498 * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.
499 * @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag.
500 * @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.
501 * @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.
502 * @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag.
503 * @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag.
504 * @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.
505 * @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.
506 * @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag.
507 * @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag.
508 * @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.
509 * @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.
510 * @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag.
511 * @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag.
512 * @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.
513 * @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.
514 * @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag.
515 * @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag.
516 * @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.
517 * @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.
518 * @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag.
519 * @retval None
520 */
\ In section .text, align 2, keep-with-next
521 void DMA_ClearFlag(uint32_t DMA_FLAG)
522 {
523 /* Check the parameters */
524 assert_param(IS_DMA_CLEAR_FLAG(DMA_FLAG));
525 /* Calculate the used DMA */
526
527 if ((DMA_FLAG & FLAG_Mask) != (uint32_t)RESET)
\ DMA_ClearFlag:
\ 00000000 C100 LSLS R1,R0,#+3
\ 00000002 02D5 BPL.N ??DMA_ClearFlag_0
528 {
529 /* Clear the selected DMA flags */
530 DMA2->IFCR = DMA_FLAG;
\ 00000004 .... LDR.N R1,??DataTable5_9 ;; 0x40020404
\ 00000006 0860 STR R0,[R1, #+0]
\ 00000008 01E0 B.N ??DMA_ClearFlag_1
531 }
532 else
533 {
534 /* Clear the selected DMA flags */
535 DMA1->IFCR = DMA_FLAG;
\ ??DMA_ClearFlag_0:
\ 0000000A .... LDR.N R1,??DataTable5_1 ;; 0x40020004
\ 0000000C 0860 STR R0,[R1, #+0]
536 }
537 }
\ ??DMA_ClearFlag_1:
\ 0000000E 7047 BX LR ;; return
538
539 /**
540 * @brief Checks whether the specified DMAy Channelx interrupt has occurred or not.
541 * @param DMA_IT: specifies the DMA interrupt source to check.
542 * This parameter can be one of the following values:
543 * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.
544 * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
545 * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
546 * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
547 * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.
548 * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
549 * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
550 * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
551 * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.
552 * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
553 * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
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