📄 stm32f10x_dma.lst
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235
236 /* Write to DMAy Channelx CCR */
237 DMAy_Channelx->CCR = tmpreg;
\ 0000002C 0260 STR R2,[R0, #+0]
238
239 /*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/
240 /* Write to DMAy Channelx CNDTR */
241 DMAy_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize;
\ 0000002E CB68 LDR R3,[R1, #+12]
\ 00000030 4360 STR R3,[R0, #+4]
242
243 /*--------------------------- DMAy Channelx CPAR Configuration ----------------*/
244 /* Write to DMAy Channelx CPAR */
245 DMAy_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr;
\ 00000032 0B68 LDR R3,[R1, #+0]
\ 00000034 8360 STR R3,[R0, #+8]
246
247 /*--------------------------- DMAy Channelx CMAR Configuration ----------------*/
248 /* Write to DMAy Channelx CMAR */
249 DMAy_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr;
\ 00000036 4B68 LDR R3,[R1, #+4]
\ 00000038 C360 STR R3,[R0, #+12]
250 }
\ 0000003A 10BC POP {R4}
\ 0000003C 7047 BX LR ;; return
251
252 /**
253 * @brief Fills each DMA_InitStruct member with its default value.
254 * @param DMA_InitStruct : pointer to a DMA_InitTypeDef structure which will
255 * be initialized.
256 * @retval None
257 */
\ In section .text, align 2, keep-with-next
258 void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct)
259 {
260 /*-------------- Reset DMA init structure parameters values ------------------*/
261 /* Initialize the DMA_PeripheralBaseAddr member */
262 DMA_InitStruct->DMA_PeripheralBaseAddr = 0;
\ DMA_StructInit:
\ 00000000 0021 MOVS R1,#+0
\ 00000002 0160 STR R1,[R0, #+0]
263 /* Initialize the DMA_MemoryBaseAddr member */
264 DMA_InitStruct->DMA_MemoryBaseAddr = 0;
\ 00000004 0021 MOVS R1,#+0
\ 00000006 4160 STR R1,[R0, #+4]
265 /* Initialize the DMA_DIR member */
266 DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC;
\ 00000008 0021 MOVS R1,#+0
\ 0000000A 8160 STR R1,[R0, #+8]
267 /* Initialize the DMA_BufferSize member */
268 DMA_InitStruct->DMA_BufferSize = 0;
\ 0000000C 0021 MOVS R1,#+0
\ 0000000E C160 STR R1,[R0, #+12]
269 /* Initialize the DMA_PeripheralInc member */
270 DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable;
\ 00000010 0021 MOVS R1,#+0
\ 00000012 0161 STR R1,[R0, #+16]
271 /* Initialize the DMA_MemoryInc member */
272 DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable;
\ 00000014 0021 MOVS R1,#+0
\ 00000016 4161 STR R1,[R0, #+20]
273 /* Initialize the DMA_PeripheralDataSize member */
274 DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
\ 00000018 0021 MOVS R1,#+0
\ 0000001A 8161 STR R1,[R0, #+24]
275 /* Initialize the DMA_MemoryDataSize member */
276 DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
\ 0000001C 0021 MOVS R1,#+0
\ 0000001E C161 STR R1,[R0, #+28]
277 /* Initialize the DMA_Mode member */
278 DMA_InitStruct->DMA_Mode = DMA_Mode_Normal;
\ 00000020 0021 MOVS R1,#+0
\ 00000022 0162 STR R1,[R0, #+32]
279 /* Initialize the DMA_Priority member */
280 DMA_InitStruct->DMA_Priority = DMA_Priority_Low;
\ 00000024 0021 MOVS R1,#+0
\ 00000026 4162 STR R1,[R0, #+36]
281 /* Initialize the DMA_M2M member */
282 DMA_InitStruct->DMA_M2M = DMA_M2M_Disable;
\ 00000028 0021 MOVS R1,#+0
\ 0000002A 8162 STR R1,[R0, #+40]
283 }
\ 0000002C 7047 BX LR ;; return
284
285 /**
286 * @brief Enables or disables the specified DMAy Channelx.
287 * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
288 * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
289 * @param NewState: new state of the DMAy Channelx.
290 * This parameter can be: ENABLE or DISABLE.
291 * @retval None
292 */
\ In section .text, align 2, keep-with-next
293 void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState)
294 {
295 /* Check the parameters */
296 assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
297 assert_param(IS_FUNCTIONAL_STATE(NewState));
298
299 if (NewState != DISABLE)
\ DMA_Cmd:
\ 00000000 C9B2 UXTB R1,R1 ;; ZeroExt R1,R1,#+24,#+24
\ 00000002 0029 CMP R1,#+0
\ 00000004 04D0 BEQ.N ??DMA_Cmd_0
300 {
301 /* Enable the selected DMAy Channelx */
302 DMAy_Channelx->CCR |= DMA_CCR1_EN;
\ 00000006 0268 LDR R2,[R0, #+0]
\ 00000008 52F00102 ORRS R2,R2,#0x1
\ 0000000C 0260 STR R2,[R0, #+0]
\ 0000000E 04E0 B.N ??DMA_Cmd_1
303 }
304 else
305 {
306 /* Disable the selected DMAy Channelx */
307 DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN);
\ ??DMA_Cmd_0:
\ 00000010 0268 LDR R2,[R0, #+0]
\ 00000012 4FF6FE73 MOVW R3,#+65534
\ 00000016 1A40 ANDS R2,R3,R2
\ 00000018 0260 STR R2,[R0, #+0]
308 }
309 }
\ ??DMA_Cmd_1:
\ 0000001A 7047 BX LR ;; return
310
311 /**
312 * @brief Enables or disables the specified DMAy Channelx interrupts.
313 * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
314 * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
315 * @param DMA_IT: specifies the DMA interrupts sources to be enabled
316 * or disabled.
317 * This parameter can be any combination of the following values:
318 * @arg DMA_IT_TC: Transfer complete interrupt mask
319 * @arg DMA_IT_HT: Half transfer interrupt mask
320 * @arg DMA_IT_TE: Transfer error interrupt mask
321 * @param NewState: new state of the specified DMA interrupts.
322 * This parameter can be: ENABLE or DISABLE.
323 * @retval None
324 */
\ In section .text, align 2, keep-with-next
325 void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState)
326 {
327 /* Check the parameters */
328 assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
329 assert_param(IS_DMA_CONFIG_IT(DMA_IT));
330 assert_param(IS_FUNCTIONAL_STATE(NewState));
331 if (NewState != DISABLE)
\ DMA_ITConfig:
\ 00000000 D2B2 UXTB R2,R2 ;; ZeroExt R2,R2,#+24,#+24
\ 00000002 002A CMP R2,#+0
\ 00000004 03D0 BEQ.N ??DMA_ITConfig_0
332 {
333 /* Enable the selected DMA interrupts */
334 DMAy_Channelx->CCR |= DMA_IT;
\ 00000006 0368 LDR R3,[R0, #+0]
\ 00000008 0B43 ORRS R3,R1,R3
\ 0000000A 0360 STR R3,[R0, #+0]
\ 0000000C 02E0 B.N ??DMA_ITConfig_1
335 }
336 else
337 {
338 /* Disable the selected DMA interrupts */
339 DMAy_Channelx->CCR &= ~DMA_IT;
\ ??DMA_ITConfig_0:
\ 0000000E 0368 LDR R3,[R0, #+0]
\ 00000010 8B43 BICS R3,R3,R1
\ 00000012 0360 STR R3,[R0, #+0]
340 }
341 }
\ ??DMA_ITConfig_1:
\ 00000014 7047 BX LR ;; return
342
343 /**
344 * @brief Sets the number of data units in the current DMAy Channelx transfer.
345 * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
346 * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
347 * @param DataNumber: The number of data units in the current DMAy Channelx
348 * transfer.
349 * @note This function can only be used when the DMAy_Channelx is disabled.
350 * @retval None.
351 */
\ In section .text, align 2, keep-with-next
352 void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber)
353 {
354 /* Check the parameters */
355 assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
356
357 /*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/
358 /* Write to DMAy Channelx CNDTR */
359 DMAy_Channelx->CNDTR = DataNumber;
\ DMA_SetCurrDataCounter:
\ 00000000 89B2 UXTH R1,R1 ;; ZeroExt R1,R1,#+16,#+16
\ 00000002 4160 STR R1,[R0, #+4]
360 }
\ 00000004 7047 BX LR ;; return
361
362 /**
363 * @brief Returns the number of remaining data units in the current
364 * DMAy Channelx transfer.
365 * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
366 * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
367 * @retval The number of remaining data units in the current DMAy Channelx
368 * transfer.
369 */
\ In section .text, align 2, keep-with-next
370 uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx)
371 {
372 /* Check the parameters */
373 assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
374 /* Return the number of remaining data units for DMAy Channelx */
375 return ((uint16_t)(DMAy_Channelx->CNDTR));
\ DMA_GetCurrDataCounter:
\ 00000000 4068 LDR R0,[R0, #+4]
\ 00000002 80B2 UXTH R0,R0 ;; ZeroExt R0,R0,#+16,#+16
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