📄 stm32f10x_dma.lst
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\ 00000046 06D1 BNE.N ??DMA_DeInit_3
138 {
139 /* Reset interrupt pending bits for DMA1 Channel3 */
140 DMA1->IFCR |= DMA1_Channel3_IT_Mask;
\ 00000048 .... LDR.N R1,??DataTable5_1 ;; 0x40020004
\ 0000004A 0968 LDR R1,[R1, #+0]
\ 0000004C 51F47061 ORRS R1,R1,#0xF00
\ 00000050 .... LDR.N R2,??DataTable5_1 ;; 0x40020004
\ 00000052 1160 STR R1,[R2, #+0]
\ 00000054 58E0 B.N ??DMA_DeInit_1
141 }
142 else if (DMAy_Channelx == DMA1_Channel4)
\ ??DMA_DeInit_3:
\ 00000056 .... LDR.N R1,??DataTable5_4 ;; 0x40020044
\ 00000058 8842 CMP R0,R1
\ 0000005A 06D1 BNE.N ??DMA_DeInit_4
143 {
144 /* Reset interrupt pending bits for DMA1 Channel4 */
145 DMA1->IFCR |= DMA1_Channel4_IT_Mask;
\ 0000005C .... LDR.N R1,??DataTable5_1 ;; 0x40020004
\ 0000005E 0968 LDR R1,[R1, #+0]
\ 00000060 51F47041 ORRS R1,R1,#0xF000
\ 00000064 .... LDR.N R2,??DataTable5_1 ;; 0x40020004
\ 00000066 1160 STR R1,[R2, #+0]
\ 00000068 4EE0 B.N ??DMA_DeInit_1
146 }
147 else if (DMAy_Channelx == DMA1_Channel5)
\ ??DMA_DeInit_4:
\ 0000006A .... LDR.N R1,??DataTable5_5 ;; 0x40020058
\ 0000006C 8842 CMP R0,R1
\ 0000006E 06D1 BNE.N ??DMA_DeInit_5
148 {
149 /* Reset interrupt pending bits for DMA1 Channel5 */
150 DMA1->IFCR |= DMA1_Channel5_IT_Mask;
\ 00000070 .... LDR.N R1,??DataTable5_1 ;; 0x40020004
\ 00000072 0968 LDR R1,[R1, #+0]
\ 00000074 51F47021 ORRS R1,R1,#0xF0000
\ 00000078 .... LDR.N R2,??DataTable5_1 ;; 0x40020004
\ 0000007A 1160 STR R1,[R2, #+0]
\ 0000007C 44E0 B.N ??DMA_DeInit_1
151 }
152 else if (DMAy_Channelx == DMA1_Channel6)
\ ??DMA_DeInit_5:
\ 0000007E .... LDR.N R1,??DataTable5_6 ;; 0x4002006c
\ 00000080 8842 CMP R0,R1
\ 00000082 06D1 BNE.N ??DMA_DeInit_6
153 {
154 /* Reset interrupt pending bits for DMA1 Channel6 */
155 DMA1->IFCR |= DMA1_Channel6_IT_Mask;
\ 00000084 .... LDR.N R1,??DataTable5_1 ;; 0x40020004
\ 00000086 0968 LDR R1,[R1, #+0]
\ 00000088 51F47001 ORRS R1,R1,#0xF00000
\ 0000008C .... LDR.N R2,??DataTable5_1 ;; 0x40020004
\ 0000008E 1160 STR R1,[R2, #+0]
\ 00000090 3AE0 B.N ??DMA_DeInit_1
156 }
157 else if (DMAy_Channelx == DMA1_Channel7)
\ ??DMA_DeInit_6:
\ 00000092 .... LDR.N R1,??DataTable5_7 ;; 0x40020080
\ 00000094 8842 CMP R0,R1
\ 00000096 06D1 BNE.N ??DMA_DeInit_7
158 {
159 /* Reset interrupt pending bits for DMA1 Channel7 */
160 DMA1->IFCR |= DMA1_Channel7_IT_Mask;
\ 00000098 .... LDR.N R1,??DataTable5_1 ;; 0x40020004
\ 0000009A 0968 LDR R1,[R1, #+0]
\ 0000009C 51F07061 ORRS R1,R1,#0xF000000
\ 000000A0 .... LDR.N R2,??DataTable5_1 ;; 0x40020004
\ 000000A2 1160 STR R1,[R2, #+0]
\ 000000A4 30E0 B.N ??DMA_DeInit_1
161 }
162 else if (DMAy_Channelx == DMA2_Channel1)
\ ??DMA_DeInit_7:
\ 000000A6 .... LDR.N R1,??DataTable5_8 ;; 0x40020408
\ 000000A8 8842 CMP R0,R1
\ 000000AA 06D1 BNE.N ??DMA_DeInit_8
163 {
164 /* Reset interrupt pending bits for DMA2 Channel1 */
165 DMA2->IFCR |= DMA2_Channel1_IT_Mask;
\ 000000AC .... LDR.N R1,??DataTable5_9 ;; 0x40020404
\ 000000AE 0968 LDR R1,[R1, #+0]
\ 000000B0 51F00F01 ORRS R1,R1,#0xF
\ 000000B4 .... LDR.N R2,??DataTable5_9 ;; 0x40020404
\ 000000B6 1160 STR R1,[R2, #+0]
\ 000000B8 26E0 B.N ??DMA_DeInit_1
166 }
167 else if (DMAy_Channelx == DMA2_Channel2)
\ ??DMA_DeInit_8:
\ 000000BA .... LDR.N R1,??DataTable5_10 ;; 0x4002041c
\ 000000BC 8842 CMP R0,R1
\ 000000BE 06D1 BNE.N ??DMA_DeInit_9
168 {
169 /* Reset interrupt pending bits for DMA2 Channel2 */
170 DMA2->IFCR |= DMA2_Channel2_IT_Mask;
\ 000000C0 .... LDR.N R1,??DataTable5_9 ;; 0x40020404
\ 000000C2 0968 LDR R1,[R1, #+0]
\ 000000C4 51F0F001 ORRS R1,R1,#0xF0
\ 000000C8 .... LDR.N R2,??DataTable5_9 ;; 0x40020404
\ 000000CA 1160 STR R1,[R2, #+0]
\ 000000CC 1CE0 B.N ??DMA_DeInit_1
171 }
172 else if (DMAy_Channelx == DMA2_Channel3)
\ ??DMA_DeInit_9:
\ 000000CE .... LDR.N R1,??DataTable5_11 ;; 0x40020430
\ 000000D0 8842 CMP R0,R1
\ 000000D2 06D1 BNE.N ??DMA_DeInit_10
173 {
174 /* Reset interrupt pending bits for DMA2 Channel3 */
175 DMA2->IFCR |= DMA2_Channel3_IT_Mask;
\ 000000D4 .... LDR.N R1,??DataTable5_9 ;; 0x40020404
\ 000000D6 0968 LDR R1,[R1, #+0]
\ 000000D8 51F47061 ORRS R1,R1,#0xF00
\ 000000DC .... LDR.N R2,??DataTable5_9 ;; 0x40020404
\ 000000DE 1160 STR R1,[R2, #+0]
\ 000000E0 12E0 B.N ??DMA_DeInit_1
176 }
177 else if (DMAy_Channelx == DMA2_Channel4)
\ ??DMA_DeInit_10:
\ 000000E2 .... LDR.N R1,??DataTable5_12 ;; 0x40020444
\ 000000E4 8842 CMP R0,R1
\ 000000E6 06D1 BNE.N ??DMA_DeInit_11
178 {
179 /* Reset interrupt pending bits for DMA2 Channel4 */
180 DMA2->IFCR |= DMA2_Channel4_IT_Mask;
\ 000000E8 .... LDR.N R1,??DataTable5_9 ;; 0x40020404
\ 000000EA 0968 LDR R1,[R1, #+0]
\ 000000EC 51F47041 ORRS R1,R1,#0xF000
\ 000000F0 .... LDR.N R2,??DataTable5_9 ;; 0x40020404
\ 000000F2 1160 STR R1,[R2, #+0]
\ 000000F4 08E0 B.N ??DMA_DeInit_1
181 }
182 else
183 {
184 if (DMAy_Channelx == DMA2_Channel5)
\ ??DMA_DeInit_11:
\ 000000F6 .... LDR.N R1,??DataTable5_13 ;; 0x40020458
\ 000000F8 8842 CMP R0,R1
\ 000000FA 05D1 BNE.N ??DMA_DeInit_1
185 {
186 /* Reset interrupt pending bits for DMA2 Channel5 */
187 DMA2->IFCR |= DMA2_Channel5_IT_Mask;
\ 000000FC .... LDR.N R1,??DataTable5_9 ;; 0x40020404
\ 000000FE 0968 LDR R1,[R1, #+0]
\ 00000100 51F47021 ORRS R1,R1,#0xF0000
\ 00000104 .... LDR.N R2,??DataTable5_9 ;; 0x40020404
\ 00000106 1160 STR R1,[R2, #+0]
188 }
189 }
190 }
\ ??DMA_DeInit_1:
\ 00000108 7047 BX LR ;; return
191
192 /**
193 * @brief Initializes the DMAy Channelx according to the specified
194 * parameters in the DMA_InitStruct.
195 * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
196 * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
197 * @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure that
198 * contains the configuration information for the specified DMA Channel.
199 * @retval None
200 */
\ In section .text, align 2, keep-with-next
201 void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct)
202 {
\ DMA_Init:
\ 00000000 10B4 PUSH {R4}
203 uint32_t tmpreg = 0;
\ 00000002 0022 MOVS R2,#+0
204
205 /* Check the parameters */
206 assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
207 assert_param(IS_DMA_DIR(DMA_InitStruct->DMA_DIR));
208 assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize));
209 assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc));
210 assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc));
211 assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize));
212 assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize));
213 assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode));
214 assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority));
215 assert_param(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M));
216
217 /*--------------------------- DMAy Channelx CCR Configuration -----------------*/
218 /* Get the DMAy_Channelx CCR value */
219 tmpreg = DMAy_Channelx->CCR;
\ 00000004 0368 LDR R3,[R0, #+0]
\ 00000006 1A00 MOVS R2,R3
220 /* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */
221 tmpreg &= CCR_CLEAR_Mask;
\ 00000008 .... LDR.N R3,??DataTable5_14 ;; 0xffff800f
\ 0000000A 1A40 ANDS R2,R3,R2
222 /* Configure DMAy Channelx: data transfer, data size, priority level and mode */
223 /* Set DIR bit according to DMA_DIR value */
224 /* Set CIRC bit according to DMA_Mode value */
225 /* Set PINC bit according to DMA_PeripheralInc value */
226 /* Set MINC bit according to DMA_MemoryInc value */
227 /* Set PSIZE bits according to DMA_PeripheralDataSize value */
228 /* Set MSIZE bits according to DMA_MemoryDataSize value */
229 /* Set PL bits according to DMA_Priority value */
230 /* Set the MEM2MEM bit according to DMA_M2M value */
231 tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode |
232 DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |
233 DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize |
234 DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M;
\ 0000000C 8B68 LDR R3,[R1, #+8]
\ 0000000E 0C6A LDR R4,[R1, #+32]
\ 00000010 2343 ORRS R3,R4,R3
\ 00000012 0C69 LDR R4,[R1, #+16]
\ 00000014 2343 ORRS R3,R4,R3
\ 00000016 4C69 LDR R4,[R1, #+20]
\ 00000018 2343 ORRS R3,R4,R3
\ 0000001A 8C69 LDR R4,[R1, #+24]
\ 0000001C 2343 ORRS R3,R4,R3
\ 0000001E CC69 LDR R4,[R1, #+28]
\ 00000020 2343 ORRS R3,R4,R3
\ 00000022 4C6A LDR R4,[R1, #+36]
\ 00000024 2343 ORRS R3,R4,R3
\ 00000026 8C6A LDR R4,[R1, #+40]
\ 00000028 2343 ORRS R3,R4,R3
\ 0000002A 1A43 ORRS R2,R3,R2
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