📄 stm32f10x_dma.lst
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###############################################################################
# #
# IAR ANSI C/C++ Compiler V6.10.2.52244/W32 for ARM 07/Aug/2011 12:10:35 #
# Copyright 1999-2010 IAR Systems AB. #
# #
# Cpu mode = thumb #
# Endian = little #
# Source file = F:\stm32\我的程序\Micrium\Software\EWARM\BSP\ST\STM32F10 #
# x_StdPeriph_Driver\src\stm32f10x_dma.c #
# Command line = F:\stm32\我的程序\Micrium\Software\EWARM\BSP\ST\STM32F10 #
# x_StdPeriph_Driver\src\stm32f10x_dma.c -D #
# USE_STDPERIPH_DRIVER -D STM32F10X_CL -lCN #
# F:\stm32\我的程序\Micrium\Software\EWARM\OS-II\Flash\Lis #
# t\ -o F:\stm32\我的程序\Micrium\Software\EWARM\OS-II\Fla #
# sh\Obj\ --no_cse --no_unroll --no_inline #
# --no_code_motion --no_tbaa --no_clustering #
# --no_scheduling --debug --endian=little --cpu=Cortex-M3 #
# -e --fpu=None --dlib_config #
# D:\arm\INC\c\DLib_Config_Normal.h -I #
# F:\stm32\我的程序\Micrium\Software\EWARM\OS-II\APP\ -I #
# F:\stm32\我的程序\Micrium\Software\EWARM\OS-II\..\BSP\ #
# -I F:\stm32\我的程序\Micrium\Software\EWARM\OS-II\..\BSP #
# \ST\CMSIS\CM3\CoreSupport\ -I #
# F:\stm32\我的程序\Micrium\Software\EWARM\OS-II\..\BSP\ST #
# \CMSIS\CM3\DeviceSupport\ST\STM32F10x\ -I #
# F:\stm32\我的程序\Micrium\Software\EWARM\OS-II\..\BSP\ST #
# \STM32F10x_StdPeriph_Driver\inc\ -I #
# F:\stm32\我的程序\Micrium\Software\EWARM\OS-II\..\BSP\uC #
# OS-II\ -I F:\stm32\我的程序\Micrium\Software\EWARM\OS-II #
# \..\..\uCOS-II\Ports\ARM-Cortex-M3\Generic\IAR\ -I #
# F:\stm32\我的程序\Micrium\Software\EWARM\OS-II\..\..\uCO #
# S-II\Source\ -I F:\stm32\我的程序\Micrium\Software\EWARM #
# \OS-II\..\..\uC-LIB\ -I F:\stm32\我的程序\Micrium\Softwa #
# re\EWARM\OS-II\..\..\uC-LIB\Ports\ARM-Cortex-M3\IAR\ -I #
# F:\stm32\我的程序\Micrium\Software\EWARM\OS-II\..\..\uC- #
# CPU\ -I F:\stm32\我的程序\Micrium\Software\EWARM\OS-II\. #
# .\..\uC-CPU\ARM-Cortex-M3\IAR\ -On --use_c++_inline #
# List file = F:\stm32\我的程序\Micrium\Software\EWARM\OS-II\Flash\Lis #
# t\stm32f10x_dma.lst #
# Object file = F:\stm32\我的程序\Micrium\Software\EWARM\OS-II\Flash\Obj #
# \stm32f10x_dma.o #
# #
# #
###############################################################################
F:\stm32\我的程序\Micrium\Software\EWARM\BSP\ST\STM32F10x_StdPeriph_Driver\src\stm32f10x_dma.c
1 /**
2 ******************************************************************************
3 * @file stm32f10x_dma.c
4 * @author MCD Application Team
5 * @version V3.4.0
6 * @date 10/15/2010
7 * @brief This file provides all the DMA firmware functions.
8 ******************************************************************************
9 * @copy
10 *
11 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
12 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
13 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
14 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
15 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
16 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
17 *
18 * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
19 */
20
21 /* Includes ------------------------------------------------------------------*/
22 #include "stm32f10x_dma.h"
23 #include "stm32f10x_rcc.h"
24
25 /** @addtogroup STM32F10x_StdPeriph_Driver
26 * @{
27 */
28
29 /** @defgroup DMA
30 * @brief DMA driver modules
31 * @{
32 */
33
34 /** @defgroup DMA_Private_TypesDefinitions
35 * @{
36 */
37 /**
38 * @}
39 */
40
41 /** @defgroup DMA_Private_Defines
42 * @{
43 */
44
45
46 /* DMA1 Channelx interrupt pending bit masks */
47 #define DMA1_Channel1_IT_Mask ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1))
48 #define DMA1_Channel2_IT_Mask ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2))
49 #define DMA1_Channel3_IT_Mask ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3))
50 #define DMA1_Channel4_IT_Mask ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4))
51 #define DMA1_Channel5_IT_Mask ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5))
52 #define DMA1_Channel6_IT_Mask ((uint32_t)(DMA_ISR_GIF6 | DMA_ISR_TCIF6 | DMA_ISR_HTIF6 | DMA_ISR_TEIF6))
53 #define DMA1_Channel7_IT_Mask ((uint32_t)(DMA_ISR_GIF7 | DMA_ISR_TCIF7 | DMA_ISR_HTIF7 | DMA_ISR_TEIF7))
54
55 /* DMA2 Channelx interrupt pending bit masks */
56 #define DMA2_Channel1_IT_Mask ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1))
57 #define DMA2_Channel2_IT_Mask ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2))
58 #define DMA2_Channel3_IT_Mask ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3))
59 #define DMA2_Channel4_IT_Mask ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4))
60 #define DMA2_Channel5_IT_Mask ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5))
61
62 /* DMA2 FLAG mask */
63 #define FLAG_Mask ((uint32_t)0x10000000)
64
65 /* DMA registers Masks */
66 #define CCR_CLEAR_Mask ((uint32_t)0xFFFF800F)
67
68 /**
69 * @}
70 */
71
72 /** @defgroup DMA_Private_Macros
73 * @{
74 */
75
76 /**
77 * @}
78 */
79
80 /** @defgroup DMA_Private_Variables
81 * @{
82 */
83
84 /**
85 * @}
86 */
87
88 /** @defgroup DMA_Private_FunctionPrototypes
89 * @{
90 */
91
92 /**
93 * @}
94 */
95
96 /** @defgroup DMA_Private_Functions
97 * @{
98 */
99
100 /**
101 * @brief Deinitializes the DMAy Channelx registers to their default reset
102 * values.
103 * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
104 * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
105 * @retval None
106 */
\ In section .text, align 2, keep-with-next
107 void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx)
108 {
109 /* Check the parameters */
110 assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
111
112 /* Disable the selected DMAy Channelx */
113 DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN);
\ DMA_DeInit:
\ 00000000 0168 LDR R1,[R0, #+0]
\ 00000002 4FF6FE72 MOVW R2,#+65534
\ 00000006 1140 ANDS R1,R2,R1
\ 00000008 0160 STR R1,[R0, #+0]
114
115 /* Reset DMAy Channelx control register */
116 DMAy_Channelx->CCR = 0;
\ 0000000A 0021 MOVS R1,#+0
\ 0000000C 0160 STR R1,[R0, #+0]
117
118 /* Reset DMAy Channelx remaining bytes register */
119 DMAy_Channelx->CNDTR = 0;
\ 0000000E 0021 MOVS R1,#+0
\ 00000010 4160 STR R1,[R0, #+4]
120
121 /* Reset DMAy Channelx peripheral address register */
122 DMAy_Channelx->CPAR = 0;
\ 00000012 0021 MOVS R1,#+0
\ 00000014 8160 STR R1,[R0, #+8]
123
124 /* Reset DMAy Channelx memory address register */
125 DMAy_Channelx->CMAR = 0;
\ 00000016 0021 MOVS R1,#+0
\ 00000018 C160 STR R1,[R0, #+12]
126
127 if (DMAy_Channelx == DMA1_Channel1)
\ 0000001A .... LDR.N R1,??DataTable5 ;; 0x40020008
\ 0000001C 8842 CMP R0,R1
\ 0000001E 06D1 BNE.N ??DMA_DeInit_0
128 {
129 /* Reset interrupt pending bits for DMA1 Channel1 */
130 DMA1->IFCR |= DMA1_Channel1_IT_Mask;
\ 00000020 .... LDR.N R1,??DataTable5_1 ;; 0x40020004
\ 00000022 0968 LDR R1,[R1, #+0]
\ 00000024 51F00F01 ORRS R1,R1,#0xF
\ 00000028 .... LDR.N R2,??DataTable5_1 ;; 0x40020004
\ 0000002A 1160 STR R1,[R2, #+0]
\ 0000002C 6CE0 B.N ??DMA_DeInit_1
131 }
132 else if (DMAy_Channelx == DMA1_Channel2)
\ ??DMA_DeInit_0:
\ 0000002E .... LDR.N R1,??DataTable5_2 ;; 0x4002001c
\ 00000030 8842 CMP R0,R1
\ 00000032 06D1 BNE.N ??DMA_DeInit_2
133 {
134 /* Reset interrupt pending bits for DMA1 Channel2 */
135 DMA1->IFCR |= DMA1_Channel2_IT_Mask;
\ 00000034 .... LDR.N R1,??DataTable5_1 ;; 0x40020004
\ 00000036 0968 LDR R1,[R1, #+0]
\ 00000038 51F0F001 ORRS R1,R1,#0xF0
\ 0000003C .... LDR.N R2,??DataTable5_1 ;; 0x40020004
\ 0000003E 1160 STR R1,[R2, #+0]
\ 00000040 62E0 B.N ??DMA_DeInit_1
136 }
137 else if (DMAy_Channelx == DMA1_Channel3)
\ ??DMA_DeInit_2:
\ 00000042 .... LDR.N R1,??DataTable5_3 ;; 0x40020030
\ 00000044 8842 CMP R0,R1
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