📄 stm32f10x_tim.lst
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\ 00000046 03D0 BEQ.N ??TIM_OC3Init_0
\ 00000048 ........ LDR.W R5,??DataTable10_5 ;; 0x40013400
\ 0000004C A842 CMP R0,R5
\ 0000004E 17D1 BNE.N ??TIM_OC3Init_1
477 {
478 assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
479 assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
480 assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
481 assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
482
483 /* Reset the Output N Polarity level */
484 tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3NP));
\ ??TIM_OC3Init_0:
\ 00000050 4FF2FF75 MOVW R5,#+63487
\ 00000054 2C40 ANDS R4,R5,R4
485 /* Set the Output N Polarity */
486 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8);
\ 00000056 4D89 LDRH R5,[R1, #+10]
\ 00000058 54EA0524 ORRS R4,R4,R5, LSL #+8
487 /* Reset the Output N State */
488 tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3NE));
\ 0000005C 4FF6FF35 MOVW R5,#+64511
\ 00000060 2C40 ANDS R4,R5,R4
489
490 /* Set the Output N State */
491 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8);
\ 00000062 8D88 LDRH R5,[R1, #+4]
\ 00000064 54EA0524 ORRS R4,R4,R5, LSL #+8
492 /* Reset the Ouput Compare and Output Compare N IDLE State */
493 tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS3));
\ 00000068 4EF6FF75 MOVW R5,#+61439
\ 0000006C 2A40 ANDS R2,R5,R2
494 tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS3N));
\ 0000006E 4DF6FF75 MOVW R5,#+57343
\ 00000072 2A40 ANDS R2,R5,R2
495 /* Set the Output Idle state */
496 tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4);
\ 00000074 8D89 LDRH R5,[R1, #+12]
\ 00000076 52EA0512 ORRS R2,R2,R5, LSL #+4
497 /* Set the Output N Idle state */
498 tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4);
\ 0000007A CD89 LDRH R5,[R1, #+14]
\ 0000007C 52EA0512 ORRS R2,R2,R5, LSL #+4
499 }
500 /* Write to TIMx CR2 */
501 TIMx->CR2 = tmpcr2;
\ ??TIM_OC3Init_1:
\ 00000080 8280 STRH R2,[R0, #+4]
502
503 /* Write to TIMx CCMR2 */
504 TIMx->CCMR2 = tmpccmrx;
\ 00000082 8383 STRH R3,[R0, #+28]
505
506 /* Set the Capture Compare Register value */
507 TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse;
\ 00000084 CD88 LDRH R5,[R1, #+6]
\ 00000086 8587 STRH R5,[R0, #+60]
508
509 /* Write to TIMx CCER */
510 TIMx->CCER = tmpccer;
\ 00000088 0484 STRH R4,[R0, #+32]
511 }
\ 0000008A 70BC POP {R4-R6}
\ 0000008C 7047 BX LR ;; return
512
513 /**
514 * @brief Initializes the TIMx Channel4 according to the specified
515 * parameters in the TIM_OCInitStruct.
516 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
517 * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
518 * that contains the configuration information for the specified TIM peripheral.
519 * @retval None
520 */
\ In section .text, align 2, keep-with-next
521 void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
522 {
\ TIM_OC4Init:
\ 00000000 70B4 PUSH {R4-R6}
523 uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
\ 00000002 0023 MOVS R3,#+0
\ 00000004 0024 MOVS R4,#+0
\ 00000006 0022 MOVS R2,#+0
524
525 /* Check the parameters */
526 assert_param(IS_TIM_LIST3_PERIPH(TIMx));
527 assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
528 assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
529 assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
530 /* Disable the Channel 2: Reset the CC4E Bit */
531 TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC4E));
\ 00000008 058C LDRH R5,[R0, #+32]
\ 0000000A 4EF6FF76 MOVW R6,#+61439
\ 0000000E 3540 ANDS R5,R6,R5
\ 00000010 0584 STRH R5,[R0, #+32]
532
533 /* Get the TIMx CCER register value */
534 tmpccer = TIMx->CCER;
\ 00000012 058C LDRH R5,[R0, #+32]
\ 00000014 2C00 MOVS R4,R5
535 /* Get the TIMx CR2 register value */
536 tmpcr2 = TIMx->CR2;
\ 00000016 8588 LDRH R5,[R0, #+4]
\ 00000018 2A00 MOVS R2,R5
537
538 /* Get the TIMx CCMR2 register value */
539 tmpccmrx = TIMx->CCMR2;
\ 0000001A 858B LDRH R5,[R0, #+28]
\ 0000001C 2B00 MOVS R3,R5
540
541 /* Reset the Output Compare mode and Capture/Compare selection Bits */
542 tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC4M));
\ 0000001E 48F6FF75 MOVW R5,#+36863
\ 00000022 2B40 ANDS R3,R5,R3
543 tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_CC4S));
\ 00000024 4FF6FF45 MOVW R5,#+64767
\ 00000028 2B40 ANDS R3,R5,R3
544
545 /* Select the Output Compare Mode */
546 tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);
\ 0000002A 0D88 LDRH R5,[R1, #+0]
\ 0000002C 53EA0523 ORRS R3,R3,R5, LSL #+8
547
548 /* Reset the Output Polarity level */
549 tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC4P));
\ 00000030 4DF6FF75 MOVW R5,#+57343
\ 00000034 2C40 ANDS R4,R5,R4
550 /* Set the Output Compare Polarity */
551 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12);
\ 00000036 0D89 LDRH R5,[R1, #+8]
\ 00000038 54EA0534 ORRS R4,R4,R5, LSL #+12
552
553 /* Set the Output State */
554 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12);
\ 0000003C 4D88 LDRH R5,[R1, #+2]
\ 0000003E 54EA0534 ORRS R4,R4,R5, LSL #+12
555
556 if((TIMx == TIM1) || (TIMx == TIM8))
\ 00000042 ........ LDR.W R5,??DataTable7 ;; 0x40012c00
\ 00000046 A842 CMP R0,R5
\ 00000048 03D0 BEQ.N ??TIM_OC4Init_0
\ 0000004A ........ LDR.W R5,??DataTable10_5 ;; 0x40013400
\ 0000004E A842 CMP R0,R5
\ 00000050 05D1 BNE.N ??TIM_OC4Init_1
557 {
558 assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
559 /* Reset the Ouput Compare IDLE State */
560 tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS4));
\ ??TIM_OC4Init_0:
\ 00000052 4BF6FF75 MOVW R5,#+49151
\ 00000056 2A40 ANDS R2,R5,R2
561 /* Set the Output Idle state */
562 tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6);
\ 00000058 8D89 LDRH R5,[R1, #+12]
\ 0000005A 52EA8512 ORRS R2,R2,R5, LSL #+6
563 }
564 /* Write to TIMx CR2 */
565 TIMx->CR2 = tmpcr2;
\ ??TIM_OC4Init_1:
\ 0000005E 8280 STRH R2,[R0, #+4]
566
567 /* Write to TIMx CCMR2 */
568 TIMx->CCMR2 = tmpccmrx;
\ 00000060 8383 STRH R3,[R0, #+28]
569
570 /* Set the Capture Compare Register value */
571 TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse;
\ 00000062 CD88 LDRH R5,[R1, #+6]
\ 00000064 A0F84050 STRH R5,[R0, #+64]
572
573 /* Write to TIMx CCER */
574 TIMx->CCER = tmpccer;
\ 00000068 0484 STRH R4,[R0, #+32]
575 }
\ 0000006A 70BC POP {R4-R6}
\ 0000006C 7047 BX LR ;; return
576
577 /**
578 * @brief Initializes the TIM peripheral according to the specified
579 * parameters in the TIM_ICInitStruct.
580 * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
581 * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure
582 * that contains the configuration information for the specified TIM peripheral.
583 * @retval None
584 */
\ In section .text, align 2, keep-with-next
585 void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
586 {
\ TIM_ICInit:
\ 00000000 38B5 PUSH {R3-R5,LR}
\ 00000002 0400 MOVS R4,R0
\ 00000004 0D00 MOVS R5,R1
587 /* Check the parameters */
588 assert_param(IS_TIM_CHANNEL(TIM_ICInitStruct->TIM_Channel));
589 assert_param(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection));
590 assert_param(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler));
591 assert_param(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter));
592
593 if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) ||
594 (TIMx == TIM4) ||(TIMx == TIM5))
\ 00000006 ........ LDR.W R0,??DataTable7 ;; 0x40012c00
\ 0000000A 8442 CMP R4,R0
\ 0000000C 12D0 BEQ.N ??TIM_ICInit_0
\ 0000000E ........ LDR.W R0,??DataTable9_1 ;; 0x40013400
\ 00000012 8442 CMP R4,R0
\ 00000014 0ED0 BEQ.N ??TIM_ICInit_0
\ 00000016 B4F1804F CMP R4,#+1073741824
\ 0000001A 0BD0 BEQ.N ??TIM_ICInit_0
\ 0000001C ........ LDR.W R0,??DataTable8 ;; 0x40000400
\ 00000020 8442 CMP R4,R0
\ 00000022 07D0 BEQ.N ??TIM_ICInit_0
\ 00000024 ........ LDR.W R0,??DataTable8_1 ;; 0x40000800
\ 00000028 8442 CMP R4,R0
\ 0000002A 03D0 BEQ.N ??TIM_ICInit_0
\ 0000002C ........ LDR.W R0,??DataTable8_2 ;; 0x40000c00
\ 00000030 8442 CMP R4,R0
\ 00000032 00D1 BNE.N ??TIM_ICInit_1
595 {
596 assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity));
\ ??TIM_ICInit_0:
\ 00000034 FFE7 B.N ??TIM_ICInit_2
597 }
598 else
599 {
600 assert_param(IS_TIM_IC_POLARITY_LITE(TIM_ICInitStruct->TIM_ICPolarity));
601 }
602 if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
\ ??TIM_ICInit_1:
\ ??TIM_ICInit_2:
\ 00000036 2888 LDRH R0,[R5, #+0]
\ 00000038 0028 CMP R0,#+0
\ 0000003A 0AD1 ⌨️ 快捷键说明
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