📄 stm32f10x_tim.lst
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\ 0000008C 8280 STRH R2,[R0, #+4]
340
341 /* Write to TIMx CCMR1 */
342 TIMx->CCMR1 = tmpccmrx;
\ 0000008E 0383 STRH R3,[R0, #+24]
343
344 /* Set the Capture Compare Register value */
345 TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse;
\ 00000090 CD88 LDRH R5,[R1, #+6]
\ 00000092 8586 STRH R5,[R0, #+52]
346
347 /* Write to TIMx CCER */
348 TIMx->CCER = tmpccer;
\ 00000094 0484 STRH R4,[R0, #+32]
349 }
\ 00000096 70BC POP {R4-R6}
\ 00000098 7047 BX LR ;; return
350
351 /**
352 * @brief Initializes the TIMx Channel2 according to the specified
353 * parameters in the TIM_OCInitStruct.
354 * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select
355 * the TIM peripheral.
356 * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
357 * that contains the configuration information for the specified TIM peripheral.
358 * @retval None
359 */
\ In section .text, align 2, keep-with-next
360 void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
361 {
\ TIM_OC2Init:
\ 00000000 70B4 PUSH {R4-R6}
362 uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
\ 00000002 0023 MOVS R3,#+0
\ 00000004 0024 MOVS R4,#+0
\ 00000006 0022 MOVS R2,#+0
363
364 /* Check the parameters */
365 assert_param(IS_TIM_LIST6_PERIPH(TIMx));
366 assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
367 assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
368 assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
369 /* Disable the Channel 2: Reset the CC2E Bit */
370 TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC2E));
\ 00000008 058C LDRH R5,[R0, #+32]
\ 0000000A 4FF6EF76 MOVW R6,#+65519
\ 0000000E 3540 ANDS R5,R6,R5
\ 00000010 0584 STRH R5,[R0, #+32]
371
372 /* Get the TIMx CCER register value */
373 tmpccer = TIMx->CCER;
\ 00000012 058C LDRH R5,[R0, #+32]
\ 00000014 2C00 MOVS R4,R5
374 /* Get the TIMx CR2 register value */
375 tmpcr2 = TIMx->CR2;
\ 00000016 8588 LDRH R5,[R0, #+4]
\ 00000018 2A00 MOVS R2,R5
376
377 /* Get the TIMx CCMR1 register value */
378 tmpccmrx = TIMx->CCMR1;
\ 0000001A 058B LDRH R5,[R0, #+24]
\ 0000001C 2B00 MOVS R3,R5
379
380 /* Reset the Output Compare mode and Capture/Compare selection Bits */
381 tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC2M));
\ 0000001E 48F6FF75 MOVW R5,#+36863
\ 00000022 2B40 ANDS R3,R5,R3
382 tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC2S));
\ 00000024 4FF6FF45 MOVW R5,#+64767
\ 00000028 2B40 ANDS R3,R5,R3
383
384 /* Select the Output Compare Mode */
385 tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);
\ 0000002A 0D88 LDRH R5,[R1, #+0]
\ 0000002C 53EA0523 ORRS R3,R3,R5, LSL #+8
386
387 /* Reset the Output Polarity level */
388 tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2P));
\ 00000030 4FF6DF75 MOVW R5,#+65503
\ 00000034 2C40 ANDS R4,R5,R4
389 /* Set the Output Compare Polarity */
390 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4);
\ 00000036 0D89 LDRH R5,[R1, #+8]
\ 00000038 54EA0514 ORRS R4,R4,R5, LSL #+4
391
392 /* Set the Output State */
393 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4);
\ 0000003C 4D88 LDRH R5,[R1, #+2]
\ 0000003E 54EA0514 ORRS R4,R4,R5, LSL #+4
394
395 if((TIMx == TIM1) || (TIMx == TIM8))
\ 00000042 ........ LDR.W R5,??DataTable7 ;; 0x40012c00
\ 00000046 A842 CMP R0,R5
\ 00000048 03D0 BEQ.N ??TIM_OC2Init_0
\ 0000004A ........ LDR.W R5,??DataTable10_5 ;; 0x40013400
\ 0000004E A842 CMP R0,R5
\ 00000050 17D1 BNE.N ??TIM_OC2Init_1
396 {
397 assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
398 assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
399 assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
400 assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
401
402 /* Reset the Output N Polarity level */
403 tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2NP));
\ ??TIM_OC2Init_0:
\ 00000052 4FF67F75 MOVW R5,#+65407
\ 00000056 2C40 ANDS R4,R5,R4
404 /* Set the Output N Polarity */
405 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4);
\ 00000058 4D89 LDRH R5,[R1, #+10]
\ 0000005A 54EA0514 ORRS R4,R4,R5, LSL #+4
406
407 /* Reset the Output N State */
408 tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2NE));
\ 0000005E 4FF6BF75 MOVW R5,#+65471
\ 00000062 2C40 ANDS R4,R5,R4
409 /* Set the Output N State */
410 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4);
\ 00000064 8D88 LDRH R5,[R1, #+4]
\ 00000066 54EA0514 ORRS R4,R4,R5, LSL #+4
411
412 /* Reset the Ouput Compare and Output Compare N IDLE State */
413 tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS2));
\ 0000006A 4FF6FF35 MOVW R5,#+64511
\ 0000006E 2A40 ANDS R2,R5,R2
414 tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS2N));
\ 00000070 4FF2FF75 MOVW R5,#+63487
\ 00000074 2A40 ANDS R2,R5,R2
415
416 /* Set the Output Idle state */
417 tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 2);
\ 00000076 8D89 LDRH R5,[R1, #+12]
\ 00000078 52EA8502 ORRS R2,R2,R5, LSL #+2
418 /* Set the Output N Idle state */
419 tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 2);
\ 0000007C CD89 LDRH R5,[R1, #+14]
\ 0000007E 52EA8502 ORRS R2,R2,R5, LSL #+2
420 }
421 /* Write to TIMx CR2 */
422 TIMx->CR2 = tmpcr2;
\ ??TIM_OC2Init_1:
\ 00000082 8280 STRH R2,[R0, #+4]
423
424 /* Write to TIMx CCMR1 */
425 TIMx->CCMR1 = tmpccmrx;
\ 00000084 0383 STRH R3,[R0, #+24]
426
427 /* Set the Capture Compare Register value */
428 TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse;
\ 00000086 CD88 LDRH R5,[R1, #+6]
\ 00000088 0587 STRH R5,[R0, #+56]
429
430 /* Write to TIMx CCER */
431 TIMx->CCER = tmpccer;
\ 0000008A 0484 STRH R4,[R0, #+32]
432 }
\ 0000008C 70BC POP {R4-R6}
\ 0000008E 7047 BX LR ;; return
433
434 /**
435 * @brief Initializes the TIMx Channel3 according to the specified
436 * parameters in the TIM_OCInitStruct.
437 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
438 * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
439 * that contains the configuration information for the specified TIM peripheral.
440 * @retval None
441 */
\ In section .text, align 2, keep-with-next
442 void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
443 {
\ TIM_OC3Init:
\ 00000000 70B4 PUSH {R4-R6}
444 uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
\ 00000002 0023 MOVS R3,#+0
\ 00000004 0024 MOVS R4,#+0
\ 00000006 0022 MOVS R2,#+0
445
446 /* Check the parameters */
447 assert_param(IS_TIM_LIST3_PERIPH(TIMx));
448 assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
449 assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
450 assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
451 /* Disable the Channel 2: Reset the CC2E Bit */
452 TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC3E));
\ 00000008 058C LDRH R5,[R0, #+32]
\ 0000000A 4FF6FF66 MOVW R6,#+65279
\ 0000000E 3540 ANDS R5,R6,R5
\ 00000010 0584 STRH R5,[R0, #+32]
453
454 /* Get the TIMx CCER register value */
455 tmpccer = TIMx->CCER;
\ 00000012 058C LDRH R5,[R0, #+32]
\ 00000014 2C00 MOVS R4,R5
456 /* Get the TIMx CR2 register value */
457 tmpcr2 = TIMx->CR2;
\ 00000016 8588 LDRH R5,[R0, #+4]
\ 00000018 2A00 MOVS R2,R5
458
459 /* Get the TIMx CCMR2 register value */
460 tmpccmrx = TIMx->CCMR2;
\ 0000001A 858B LDRH R5,[R0, #+28]
\ 0000001C 2B00 MOVS R3,R5
461
462 /* Reset the Output Compare mode and Capture/Compare selection Bits */
463 tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC3M));
\ 0000001E 4FF68F75 MOVW R5,#+65423
\ 00000022 2B40 ANDS R3,R5,R3
464 tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_CC3S));
\ 00000024 4FF6FC75 MOVW R5,#+65532
\ 00000028 2B40 ANDS R3,R5,R3
465 /* Select the Output Compare Mode */
466 tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
\ 0000002A 0D88 LDRH R5,[R1, #+0]
\ 0000002C 2B43 ORRS R3,R5,R3
467
468 /* Reset the Output Polarity level */
469 tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3P));
\ 0000002E 4FF6FF55 MOVW R5,#+65023
\ 00000032 2C40 ANDS R4,R5,R4
470 /* Set the Output Compare Polarity */
471 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8);
\ 00000034 0D89 LDRH R5,[R1, #+8]
\ 00000036 54EA0524 ORRS R4,R4,R5, LSL #+8
472
473 /* Set the Output State */
474 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8);
\ 0000003A 4D88 LDRH R5,[R1, #+2]
\ 0000003C 54EA0524 ORRS R4,R4,R5, LSL #+8
475
476 if((TIMx == TIM1) || (TIMx == TIM8))
\ 00000040 ........ LDR.W R5,??DataTable7 ;; 0x40012c00
\ 00000044 A842 CMP R0,R5
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