📄 stm32f10x_tim.lst
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230 assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode));
231 assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision));
232
233 tmpcr1 = TIMx->CR1;
\ 00000002 0388 LDRH R3,[R0, #+0]
\ 00000004 1A00 MOVS R2,R3
234
235 if((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM2) || (TIMx == TIM3)||
236 (TIMx == TIM4) || (TIMx == TIM5))
\ 00000006 ........ LDR.W R3,??DataTable7 ;; 0x40012c00
\ 0000000A 9842 CMP R0,R3
\ 0000000C 12D0 BEQ.N ??TIM_TimeBaseInit_0
\ 0000000E ........ LDR.W R3,??DataTable9_1 ;; 0x40013400
\ 00000012 9842 CMP R0,R3
\ 00000014 0ED0 BEQ.N ??TIM_TimeBaseInit_0
\ 00000016 B0F1804F CMP R0,#+1073741824
\ 0000001A 0BD0 BEQ.N ??TIM_TimeBaseInit_0
\ 0000001C ........ LDR.W R3,??DataTable8 ;; 0x40000400
\ 00000020 9842 CMP R0,R3
\ 00000022 07D0 BEQ.N ??TIM_TimeBaseInit_0
\ 00000024 ........ LDR.W R3,??DataTable8_1 ;; 0x40000800
\ 00000028 9842 CMP R0,R3
\ 0000002A 03D0 BEQ.N ??TIM_TimeBaseInit_0
\ 0000002C ........ LDR.W R3,??DataTable8_2 ;; 0x40000c00
\ 00000030 9842 CMP R0,R3
\ 00000032 04D1 BNE.N ??TIM_TimeBaseInit_1
237 {
238 /* Select the Counter Mode */
239 tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS)));
\ ??TIM_TimeBaseInit_0:
\ 00000034 4FF68F73 MOVW R3,#+65423
\ 00000038 1A40 ANDS R2,R3,R2
240 tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode;
\ 0000003A 4B88 LDRH R3,[R1, #+2]
\ 0000003C 1A43 ORRS R2,R3,R2
241 }
242
243 if((TIMx != TIM6) && (TIMx != TIM7))
\ ??TIM_TimeBaseInit_1:
\ 0000003E ........ LDR.W R3,??DataTable8_3 ;; 0x40001000
\ 00000042 9842 CMP R0,R3
\ 00000044 08D0 BEQ.N ??TIM_TimeBaseInit_2
\ 00000046 ........ LDR.W R3,??DataTable9 ;; 0x40001400
\ 0000004A 9842 CMP R0,R3
\ 0000004C 04D0 BEQ.N ??TIM_TimeBaseInit_2
244 {
245 /* Set the clock division */
246 tmpcr1 &= (uint16_t)(~((uint16_t)TIM_CR1_CKD));
\ 0000004E 4FF6FF43 MOVW R3,#+64767
\ 00000052 1A40 ANDS R2,R3,R2
247 tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision;
\ 00000054 CB88 LDRH R3,[R1, #+6]
\ 00000056 1A43 ORRS R2,R3,R2
248 }
249
250 TIMx->CR1 = tmpcr1;
\ ??TIM_TimeBaseInit_2:
\ 00000058 0280 STRH R2,[R0, #+0]
251
252 /* Set the Autoreload value */
253 TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ;
\ 0000005A 8B88 LDRH R3,[R1, #+4]
\ 0000005C 8385 STRH R3,[R0, #+44]
254
255 /* Set the Prescaler value */
256 TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler;
\ 0000005E 0B88 LDRH R3,[R1, #+0]
\ 00000060 0385 STRH R3,[R0, #+40]
257
258 if ((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM15)|| (TIMx == TIM16) || (TIMx == TIM17))
\ 00000062 ........ LDR.W R3,??DataTable7 ;; 0x40012c00
\ 00000066 9842 CMP R0,R3
\ 00000068 0FD0 BEQ.N ??TIM_TimeBaseInit_3
\ 0000006A ........ LDR.W R3,??DataTable9_1 ;; 0x40013400
\ 0000006E 9842 CMP R0,R3
\ 00000070 0BD0 BEQ.N ??TIM_TimeBaseInit_3
\ 00000072 ........ LDR.W R3,??DataTable10_2 ;; 0x40014000
\ 00000076 9842 CMP R0,R3
\ 00000078 07D0 BEQ.N ??TIM_TimeBaseInit_3
\ 0000007A ........ LDR.W R3,??DataTable10_3 ;; 0x40014400
\ 0000007E 9842 CMP R0,R3
\ 00000080 03D0 BEQ.N ??TIM_TimeBaseInit_3
\ 00000082 ........ LDR.W R3,??DataTable10_4 ;; 0x40014800
\ 00000086 9842 CMP R0,R3
\ 00000088 01D1 BNE.N ??TIM_TimeBaseInit_4
259 {
260 /* Set the Repetition Counter value */
261 TIMx->RCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter;
\ ??TIM_TimeBaseInit_3:
\ 0000008A 0B7A LDRB R3,[R1, #+8]
\ 0000008C 0386 STRH R3,[R0, #+48]
262 }
263
264 /* Generate an update event to reload the Prescaler and the Repetition counter
265 values immediately */
266 TIMx->EGR = TIM_PSCReloadMode_Immediate;
\ ??TIM_TimeBaseInit_4:
\ 0000008E 0123 MOVS R3,#+1
\ 00000090 8382 STRH R3,[R0, #+20]
267 }
\ 00000092 7047 BX LR ;; return
268
269 /**
270 * @brief Initializes the TIMx Channel1 according to the specified
271 * parameters in the TIM_OCInitStruct.
272 * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
273 * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
274 * that contains the configuration information for the specified TIM peripheral.
275 * @retval None
276 */
\ In section .text, align 2, keep-with-next
277 void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
278 {
\ TIM_OC1Init:
\ 00000000 70B4 PUSH {R4-R6}
279 uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
\ 00000002 0023 MOVS R3,#+0
\ 00000004 0024 MOVS R4,#+0
\ 00000006 0022 MOVS R2,#+0
280
281 /* Check the parameters */
282 assert_param(IS_TIM_LIST8_PERIPH(TIMx));
283 assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
284 assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
285 assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
286 /* Disable the Channel 1: Reset the CC1E Bit */
287 TIMx->CCER &= (uint16_t)(~(uint16_t)TIM_CCER_CC1E);
\ 00000008 058C LDRH R5,[R0, #+32]
\ 0000000A 4FF6FE76 MOVW R6,#+65534
\ 0000000E 3540 ANDS R5,R6,R5
\ 00000010 0584 STRH R5,[R0, #+32]
288 /* Get the TIMx CCER register value */
289 tmpccer = TIMx->CCER;
\ 00000012 058C LDRH R5,[R0, #+32]
\ 00000014 2C00 MOVS R4,R5
290 /* Get the TIMx CR2 register value */
291 tmpcr2 = TIMx->CR2;
\ 00000016 8588 LDRH R5,[R0, #+4]
\ 00000018 2A00 MOVS R2,R5
292
293 /* Get the TIMx CCMR1 register value */
294 tmpccmrx = TIMx->CCMR1;
\ 0000001A 058B LDRH R5,[R0, #+24]
\ 0000001C 2B00 MOVS R3,R5
295
296 /* Reset the Output Compare Mode Bits */
297 tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC1M));
\ 0000001E 4FF68F75 MOVW R5,#+65423
\ 00000022 2B40 ANDS R3,R5,R3
298 tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC1S));
\ 00000024 4FF6FC75 MOVW R5,#+65532
\ 00000028 2B40 ANDS R3,R5,R3
299
300 /* Select the Output Compare Mode */
301 tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
\ 0000002A 0D88 LDRH R5,[R1, #+0]
\ 0000002C 2B43 ORRS R3,R5,R3
302
303 /* Reset the Output Polarity level */
304 tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1P));
\ 0000002E 4FF6FD75 MOVW R5,#+65533
\ 00000032 2C40 ANDS R4,R5,R4
305 /* Set the Output Compare Polarity */
306 tmpccer |= TIM_OCInitStruct->TIM_OCPolarity;
\ 00000034 0D89 LDRH R5,[R1, #+8]
\ 00000036 2C43 ORRS R4,R5,R4
307
308 /* Set the Output State */
309 tmpccer |= TIM_OCInitStruct->TIM_OutputState;
\ 00000038 4D88 LDRH R5,[R1, #+2]
\ 0000003A 2C43 ORRS R4,R5,R4
310
311 if((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM15)||
312 (TIMx == TIM16)|| (TIMx == TIM17))
\ 0000003C ........ LDR.W R5,??DataTable7 ;; 0x40012c00
\ 00000040 A842 CMP R0,R5
\ 00000042 0FD0 BEQ.N ??TIM_OC1Init_0
\ 00000044 ........ LDR.W R5,??DataTable9_1 ;; 0x40013400
\ 00000048 A842 CMP R0,R5
\ 0000004A 0BD0 BEQ.N ??TIM_OC1Init_0
\ 0000004C ........ LDR.W R5,??DataTable10_2 ;; 0x40014000
\ 00000050 A842 CMP R0,R5
\ 00000052 07D0 BEQ.N ??TIM_OC1Init_0
\ 00000054 ........ LDR.W R5,??DataTable10_3 ;; 0x40014400
\ 00000058 A842 CMP R0,R5
\ 0000005A 03D0 BEQ.N ??TIM_OC1Init_0
\ 0000005C ........ LDR.W R5,??DataTable10_4 ;; 0x40014800
\ 00000060 A842 CMP R0,R5
\ 00000062 13D1 BNE.N ??TIM_OC1Init_1
313 {
314 assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
315 assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
316 assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
317 assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
318
319 /* Reset the Output N Polarity level */
320 tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1NP));
\ ??TIM_OC1Init_0:
\ 00000064 4FF6F775 MOVW R5,#+65527
\ 00000068 2C40 ANDS R4,R5,R4
321 /* Set the Output N Polarity */
322 tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity;
\ 0000006A 4D89 LDRH R5,[R1, #+10]
\ 0000006C 2C43 ORRS R4,R5,R4
323
324 /* Reset the Output N State */
325 tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1NE));
\ 0000006E 4FF6FB75 MOVW R5,#+65531
\ 00000072 2C40 ANDS R4,R5,R4
326 /* Set the Output N State */
327 tmpccer |= TIM_OCInitStruct->TIM_OutputNState;
\ 00000074 8D88 LDRH R5,[R1, #+4]
\ 00000076 2C43 ORRS R4,R5,R4
328
329 /* Reset the Ouput Compare and Output Compare N IDLE State */
330 tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS1));
\ 00000078 4FF6FF65 MOVW R5,#+65279
\ 0000007C 2A40 ANDS R2,R5,R2
331 tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS1N));
\ 0000007E 4FF6FF55 MOVW R5,#+65023
\ 00000082 2A40 ANDS R2,R5,R2
332
333 /* Set the Output Idle state */
334 tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState;
\ 00000084 8D89 LDRH R5,[R1, #+12]
\ 00000086 2A43 ORRS R2,R5,R2
335 /* Set the Output N Idle state */
336 tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState;
\ 00000088 CD89 LDRH R5,[R1, #+14]
\ 0000008A 2A43 ORRS R2,R5,R2
337 }
338 /* Write to TIMx CR2 */
339 TIMx->CR2 = tmpcr2;
\ ??TIM_OC1Init_1:
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