📄 stm32f10x_spi.lst
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\ SPI_Init:
\ 00000000 10B4 PUSH {R4}
159 uint16_t tmpreg = 0;
\ 00000002 0022 MOVS R2,#+0
160
161 /* check the parameters */
162 assert_param(IS_SPI_ALL_PERIPH(SPIx));
163
164 /* Check the SPI parameters */
165 assert_param(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction));
166 assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode));
167 assert_param(IS_SPI_DATASIZE(SPI_InitStruct->SPI_DataSize));
168 assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL));
169 assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA));
170 assert_param(IS_SPI_NSS(SPI_InitStruct->SPI_NSS));
171 assert_param(IS_SPI_BAUDRATE_PRESCALER(SPI_InitStruct->SPI_BaudRatePrescaler));
172 assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit));
173 assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->SPI_CRCPolynomial));
174
175 /*---------------------------- SPIx CR1 Configuration ------------------------*/
176 /* Get the SPIx CR1 value */
177 tmpreg = SPIx->CR1;
\ 00000004 0388 LDRH R3,[R0, #+0]
\ 00000006 1A00 MOVS R2,R3
178 /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */
179 tmpreg &= CR1_CLEAR_Mask;
\ 00000008 12F44152 ANDS R2,R2,#0x3040
180 /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler
181 master/salve mode, CPOL and CPHA */
182 /* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */
183 /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */
184 /* Set LSBFirst bit according to SPI_FirstBit value */
185 /* Set BR bits according to SPI_BaudRatePrescaler value */
186 /* Set CPOL bit according to SPI_CPOL value */
187 /* Set CPHA bit according to SPI_CPHA value */
188 tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode |
189 SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL |
190 SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS |
191 SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit);
\ 0000000C 0B88 LDRH R3,[R1, #+0]
\ 0000000E 4C88 LDRH R4,[R1, #+2]
\ 00000010 2343 ORRS R3,R4,R3
\ 00000012 8C88 LDRH R4,[R1, #+4]
\ 00000014 2343 ORRS R3,R4,R3
\ 00000016 CC88 LDRH R4,[R1, #+6]
\ 00000018 2343 ORRS R3,R4,R3
\ 0000001A 0C89 LDRH R4,[R1, #+8]
\ 0000001C 2343 ORRS R3,R4,R3
\ 0000001E 4C89 LDRH R4,[R1, #+10]
\ 00000020 2343 ORRS R3,R4,R3
\ 00000022 8C89 LDRH R4,[R1, #+12]
\ 00000024 2343 ORRS R3,R4,R3
\ 00000026 CC89 LDRH R4,[R1, #+14]
\ 00000028 2343 ORRS R3,R4,R3
\ 0000002A 1A43 ORRS R2,R3,R2
192 /* Write to SPIx CR1 */
193 SPIx->CR1 = tmpreg;
\ 0000002C 0280 STRH R2,[R0, #+0]
194
195 /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
196 SPIx->I2SCFGR &= SPI_Mode_Select;
\ 0000002E 838B LDRH R3,[R0, #+28]
\ 00000030 4FF2FF74 MOVW R4,#+63487
\ 00000034 2340 ANDS R3,R4,R3
\ 00000036 8383 STRH R3,[R0, #+28]
197
198 /*---------------------------- SPIx CRCPOLY Configuration --------------------*/
199 /* Write to SPIx CRCPOLY */
200 SPIx->CRCPR = SPI_InitStruct->SPI_CRCPolynomial;
\ 00000038 0B8A LDRH R3,[R1, #+16]
\ 0000003A 0382 STRH R3,[R0, #+16]
201 }
\ 0000003C 10BC POP {R4}
\ 0000003E 7047 BX LR ;; return
202
203 /**
204 * @brief Initializes the SPIx peripheral according to the specified
205 * parameters in the I2S_InitStruct.
206 * @param SPIx: where x can be 2 or 3 to select the SPI peripheral
207 * (configured in I2S mode).
208 * @param I2S_InitStruct: pointer to an I2S_InitTypeDef structure that
209 * contains the configuration information for the specified SPI peripheral
210 * configured in I2S mode.
211 * @note
212 * The function calculates the optimal prescaler needed to obtain the most
213 * accurate audio frequency (depending on the I2S clock source, the PLL values
214 * and the product configuration). But in case the prescaler value is greater
215 * than 511, the default value (0x02) will be configured instead. *
216 * @retval None
217 */
\ In section .text, align 2, keep-with-next
218 void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct)
219 {
\ I2S_Init:
\ 00000000 2DE9F04F PUSH {R4-R11,LR}
\ 00000004 85B0 SUB SP,SP,#+20
\ 00000006 0400 MOVS R4,R0
\ 00000008 0D00 MOVS R5,R1
220 uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1;
\ 0000000A 0026 MOVS R6,#+0
\ 0000000C 0227 MOVS R7,#+2
\ 0000000E 5FF00008 MOVS R8,#+0
\ 00000012 5FF00109 MOVS R9,#+1
221 uint32_t tmp = 0;
\ 00000016 5FF0000A MOVS R10,#+0
222 RCC_ClocksTypeDef RCC_Clocks;
223 uint32_t sourceclock = 0;
\ 0000001A 5FF0000B MOVS R11,#+0
224
225 /* Check the I2S parameters */
226 assert_param(IS_SPI_23_PERIPH(SPIx));
227 assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode));
228 assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard));
229 assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat));
230 assert_param(IS_I2S_MCLK_OUTPUT(I2S_InitStruct->I2S_MCLKOutput));
231 assert_param(IS_I2S_AUDIO_FREQ(I2S_InitStruct->I2S_AudioFreq));
232 assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL));
233
234 /*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/
235 /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
236 SPIx->I2SCFGR &= I2SCFGR_CLEAR_Mask;
\ 0000001E A08B LDRH R0,[R4, #+28]
\ 00000020 4FF24001 MOVW R1,#+61504
\ 00000024 0840 ANDS R0,R1,R0
\ 00000026 A083 STRH R0,[R4, #+28]
237 SPIx->I2SPR = 0x0002;
\ 00000028 0220 MOVS R0,#+2
\ 0000002A 2084 STRH R0,[R4, #+32]
238
239 /* Get the I2SCFGR register value */
240 tmpreg = SPIx->I2SCFGR;
\ 0000002C A08B LDRH R0,[R4, #+28]
\ 0000002E 0600 MOVS R6,R0
241
242 /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/
243 if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default)
\ 00000030 A868 LDR R0,[R5, #+8]
\ 00000032 0228 CMP R0,#+2
\ 00000034 04D1 BNE.N ??I2S_Init_0
244 {
245 i2sodd = (uint16_t)0;
\ 00000036 0020 MOVS R0,#+0
\ 00000038 8046 MOV R8,R0
246 i2sdiv = (uint16_t)2;
\ 0000003A 0220 MOVS R0,#+2
\ 0000003C 0700 MOVS R7,R0
\ 0000003E 68E0 B.N ??I2S_Init_1
247 }
248 /* If the requested audio frequency is not the default, compute the prescaler */
249 else
250 {
251 /* Check the frame length (For the Prescaler computing) */
252 if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b)
\ ??I2S_Init_0:
\ 00000040 A888 LDRH R0,[R5, #+4]
\ 00000042 0028 CMP R0,#+0
\ 00000044 02D1 BNE.N ??I2S_Init_2
253 {
254 /* Packet length is 16 bits */
255 packetlength = 1;
\ 00000046 0120 MOVS R0,#+1
\ 00000048 8146 MOV R9,R0
\ 0000004A 01E0 B.N ??I2S_Init_3
256 }
257 else
258 {
259 /* Packet length is 32 bits */
260 packetlength = 2;
\ ??I2S_Init_2:
\ 0000004C 0220 MOVS R0,#+2
\ 0000004E 8146 MOV R9,R0
261 }
262
263 /* Get the I2S clock source mask depending on the peripheral number */
264 if(((uint32_t)SPIx) == SPI2_BASE)
\ ??I2S_Init_3:
\ 00000050 .... LDR.N R0,??DataTable1_1 ;; 0x40003800
\ 00000052 8442 CMP R4,R0
\ 00000054 03D1 BNE.N ??I2S_Init_4
265 {
266 /* The mask is relative to I2S2 */
267 tmp = I2S2_CLOCK_SRC;
\ 00000056 5FF40030 MOVS R0,#+131072
\ 0000005A 8246 MOV R10,R0
\ 0000005C 02E0 B.N ??I2S_Init_5
268 }
269 else
270 {
271 /* The mask is relative to I2S3 */
272 tmp = I2S3_CLOCK_SRC;
\ ??I2S_Init_4:
\ 0000005E 5FF48020 MOVS R0,#+262144
\ 00000062 8246 MOV R10,R0
273 }
274
275 /* Check the I2S clock source configuration depending on the Device:
276 Only Connectivity line devices have the PLL3 VCO clock */
277 #ifdef STM32F10X_CL
278 if((RCC->CFGR2 & tmp) != 0)
\ ??I2S_Init_5:
\ 00000064 .... LDR.N R0,??DataTable1_3 ;; 0x4002102c
\ 00000066 0068 LDR R0,[R0, #+0]
\ 00000068 10EA0A0F TST R0,R10
\ 0000006C 20D0 BEQ.N ??I2S_Init_6
279 {
280 /* Get the configuration bits of RCC PLL3 multiplier */
281 tmp = (uint32_t)((RCC->CFGR2 & I2S_MUL_MASK) >> 12);
\ 0000006E .... LDR.N R0,??DataTable1_3 ;; 0x4002102c
\ 00000070 0068 LDR R0,[R0, #+0]
\ 00000072 C0F30330 UBFX R0,R0,#+12,#+4
\ 00000076 8246 MOV R10,R0
282
283 /* Get the value of the PLL3 multiplier */
284 if((tmp > 5) && (tmp < 15))
\ 00000078 BAF1060F CMP R10,#+6
\ 0000007C 05D3 BCC.N ??I2S_Init_7
\ 0000007E BAF10F0F CMP R10,#+15
\ 00000082 02D2 BCS.N ??I2S_Init_7
285 {
286 /* Multplier is between 8 and 14 (value 15 is forbidden) */
287 tmp += 2;
\ 00000084 1AF1020A ADDS R10,R10,#+2
\ 00000088 04E0 B.N ??I2S_Init_8
288 }
289 else
290 {
291 if (tmp == 15)
\ ??I2S_Init_7:
\ 0000008A BAF10F0F CMP R10,#+15
\ 0000008E 01D1 BNE.N ??I2S_Init_8
292 {
293 /* Multiplier is 20 */
294 tmp = 20;
\ 00000090 1420 MOVS R0,#+20
\ 00000092 8246 MOV R10,R0
295 }
296 }
297 /* Get the PREDIV2 value */
298 sourceclock = (uint32_t)(((RCC->CFGR2 & I2S_DIV_MASK) >> 4) + 1);
\ ??I2S_Init_8:
\ 00000094 .... LDR.N R0,??DataTable1_3 ;; 0x4002102c
\ 00000096 0068 LDR R0,[R0, #+0]
\ 00000098 C0F30310 UBFX R0,R0,#+4,#+4
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