📄 stm32f10x_pwr.lst
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###############################################################################
# #
# IAR ANSI C/C++ Compiler V6.10.2.52244/W32 for ARM 07/Aug/2011 12:10:19 #
# Copyright 1999-2010 IAR Systems AB. #
# #
# Cpu mode = thumb #
# Endian = little #
# Source file = F:\stm32\我的程序\Micrium\Software\EWARM\BSP\ST\STM32F10 #
# x_StdPeriph_Driver\src\stm32f10x_pwr.c #
# Command line = F:\stm32\我的程序\Micrium\Software\EWARM\BSP\ST\STM32F10 #
# x_StdPeriph_Driver\src\stm32f10x_pwr.c -D #
# USE_STDPERIPH_DRIVER -D STM32F10X_CL -lCN #
# F:\stm32\我的程序\Micrium\Software\EWARM\OS-II\Flash\Lis #
# t\ -o F:\stm32\我的程序\Micrium\Software\EWARM\OS-II\Fla #
# sh\Obj\ --no_cse --no_unroll --no_inline #
# --no_code_motion --no_tbaa --no_clustering #
# --no_scheduling --debug --endian=little --cpu=Cortex-M3 #
# -e --fpu=None --dlib_config #
# D:\arm\INC\c\DLib_Config_Normal.h -I #
# F:\stm32\我的程序\Micrium\Software\EWARM\OS-II\APP\ -I #
# F:\stm32\我的程序\Micrium\Software\EWARM\OS-II\..\BSP\ #
# -I F:\stm32\我的程序\Micrium\Software\EWARM\OS-II\..\BSP #
# \ST\CMSIS\CM3\CoreSupport\ -I #
# F:\stm32\我的程序\Micrium\Software\EWARM\OS-II\..\BSP\ST #
# \CMSIS\CM3\DeviceSupport\ST\STM32F10x\ -I #
# F:\stm32\我的程序\Micrium\Software\EWARM\OS-II\..\BSP\ST #
# \STM32F10x_StdPeriph_Driver\inc\ -I #
# F:\stm32\我的程序\Micrium\Software\EWARM\OS-II\..\BSP\uC #
# OS-II\ -I F:\stm32\我的程序\Micrium\Software\EWARM\OS-II #
# \..\..\uCOS-II\Ports\ARM-Cortex-M3\Generic\IAR\ -I #
# F:\stm32\我的程序\Micrium\Software\EWARM\OS-II\..\..\uCO #
# S-II\Source\ -I F:\stm32\我的程序\Micrium\Software\EWARM #
# \OS-II\..\..\uC-LIB\ -I F:\stm32\我的程序\Micrium\Softwa #
# re\EWARM\OS-II\..\..\uC-LIB\Ports\ARM-Cortex-M3\IAR\ -I #
# F:\stm32\我的程序\Micrium\Software\EWARM\OS-II\..\..\uC- #
# CPU\ -I F:\stm32\我的程序\Micrium\Software\EWARM\OS-II\. #
# .\..\uC-CPU\ARM-Cortex-M3\IAR\ -On --use_c++_inline #
# List file = F:\stm32\我的程序\Micrium\Software\EWARM\OS-II\Flash\Lis #
# t\stm32f10x_pwr.lst #
# Object file = F:\stm32\我的程序\Micrium\Software\EWARM\OS-II\Flash\Obj #
# \stm32f10x_pwr.o #
# #
# #
###############################################################################
F:\stm32\我的程序\Micrium\Software\EWARM\BSP\ST\STM32F10x_StdPeriph_Driver\src\stm32f10x_pwr.c
1 /**
2 ******************************************************************************
3 * @file stm32f10x_pwr.c
4 * @author MCD Application Team
5 * @version V3.4.0
6 * @date 10/15/2010
7 * @brief This file provides all the PWR firmware functions.
8 ******************************************************************************
9 * @copy
10 *
11 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
12 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
13 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
14 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
15 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
16 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
17 *
18 * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
19 */
20
21 /* Includes ------------------------------------------------------------------*/
22 #include "stm32f10x_pwr.h"
\ In section .text, align 4, keep-with-next
\ static __interwork __softfp void __WFI()
\ __WFI:
\ 00000000 30BF wfi
\ 00000002 7047 BX LR ;; return
\ In section .text, align 4, keep-with-next
\ static __interwork __softfp void __WFE()
\ __WFE:
\ 00000000 20BF wfe
\ 00000002 7047 BX LR ;; return
23 #include "stm32f10x_rcc.h"
24
25 /** @addtogroup STM32F10x_StdPeriph_Driver
26 * @{
27 */
28
29 /** @defgroup PWR
30 * @brief PWR driver modules
31 * @{
32 */
33
34 /** @defgroup PWR_Private_TypesDefinitions
35 * @{
36 */
37
38 /**
39 * @}
40 */
41
42 /** @defgroup PWR_Private_Defines
43 * @{
44 */
45
46 /* --------- PWR registers bit address in the alias region ---------- */
47 #define PWR_OFFSET (PWR_BASE - PERIPH_BASE)
48
49 /* --- CR Register ---*/
50
51 /* Alias word address of DBP bit */
52 #define CR_OFFSET (PWR_OFFSET + 0x00)
53 #define DBP_BitNumber 0x08
54 #define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4))
55
56 /* Alias word address of PVDE bit */
57 #define PVDE_BitNumber 0x04
58 #define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4))
59
60 /* --- CSR Register ---*/
61
62 /* Alias word address of EWUP bit */
63 #define CSR_OFFSET (PWR_OFFSET + 0x04)
64 #define EWUP_BitNumber 0x08
65 #define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4))
66
67 /* ------------------ PWR registers bit mask ------------------------ */
68
69 /* CR register bit mask */
70 #define CR_DS_MASK ((uint32_t)0xFFFFFFFC)
71 #define CR_PLS_MASK ((uint32_t)0xFFFFFF1F)
72
73
74 /**
75 * @}
76 */
77
78 /** @defgroup PWR_Private_Macros
79 * @{
80 */
81
82 /**
83 * @}
84 */
85
86 /** @defgroup PWR_Private_Variables
87 * @{
88 */
89
90 /**
91 * @}
92 */
93
94 /** @defgroup PWR_Private_FunctionPrototypes
95 * @{
96 */
97
98 /**
99 * @}
100 */
101
102 /** @defgroup PWR_Private_Functions
103 * @{
104 */
105
106 /**
107 * @brief Deinitializes the PWR peripheral registers to their default reset values.
108 * @param None
109 * @retval None
110 */
\ In section .text, align 2, keep-with-next
111 void PWR_DeInit(void)
112 {
\ PWR_DeInit:
\ 00000000 80B5 PUSH {R7,LR}
113 RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE);
\ 00000002 0121 MOVS R1,#+1
\ 00000004 5FF08050 MOVS R0,#+268435456
\ 00000008 ........ BL RCC_APB1PeriphResetCmd
114 RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE);
\ 0000000C 0021 MOVS R1,#+0
\ 0000000E 5FF08050 MOVS R0,#+268435456
\ 00000012 ........ BL RCC_APB1PeriphResetCmd
115 }
\ 00000016 01BD POP {R0,PC} ;; return
116
117 /**
118 * @brief Enables or disables access to the RTC and backup registers.
119 * @param NewState: new state of the access to the RTC and backup registers.
120 * This parameter can be: ENABLE or DISABLE.
121 * @retval None
122 */
\ In section .text, align 2, keep-with-next
123 void PWR_BackupAccessCmd(FunctionalState NewState)
124 {
125 /* Check the parameters */
126 assert_param(IS_FUNCTIONAL_STATE(NewState));
127 *(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState;
\ PWR_BackupAccessCmd:
\ 00000000 .... LDR.N R1,??DataTable7 ;; 0x420e0020
\ 00000002 C0B2 UXTB R0,R0 ;; ZeroExt R0,R0,#+24,#+24
\ 00000004 0860 STR R0,[R1, #+0]
128 }
\ 00000006 7047 BX LR ;; return
129
130 /**
131 * @brief Enables or disables the Power Voltage Detector(PVD).
132 * @param NewState: new state of the PVD.
133 * This parameter can be: ENABLE or DISABLE.
134 * @retval None
135 */
\ In section .text, align 2, keep-with-next
136 void PWR_PVDCmd(FunctionalState NewState)
137 {
138 /* Check the parameters */
139 assert_param(IS_FUNCTIONAL_STATE(NewState));
140 *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)NewState;
\ PWR_PVDCmd:
\ 00000000 .... LDR.N R1,??DataTable7_1 ;; 0x420e0010
\ 00000002 C0B2 UXTB R0,R0 ;; ZeroExt R0,R0,#+24,#+24
\ 00000004 0860 STR R0,[R1, #+0]
141 }
\ 00000006 7047 BX LR ;; return
142
143 /**
144 * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).
145 * @param PWR_PVDLevel: specifies the PVD detection level
146 * This parameter can be one of the following values:
147 * @arg PWR_PVDLevel_2V2: PVD detection level set to 2.2V
148 * @arg PWR_PVDLevel_2V3: PVD detection level set to 2.3V
149 * @arg PWR_PVDLevel_2V4: PVD detection level set to 2.4V
150 * @arg PWR_PVDLevel_2V5: PVD detection level set to 2.5V
151 * @arg PWR_PVDLevel_2V6: PVD detection level set to 2.6V
152 * @arg PWR_PVDLevel_2V7: PVD detection level set to 2.7V
153 * @arg PWR_PVDLevel_2V8: PVD detection level set to 2.8V
154 * @arg PWR_PVDLevel_2V9: PVD detection level set to 2.9V
155 * @retval None
156 */
\ In section .text, align 2, keep-with-next
157 void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)
158 {
159 uint32_t tmpreg = 0;
\ PWR_PVDLevelConfig:
\ 00000000 0021 MOVS R1,#+0
160 /* Check the parameters */
161 assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel));
162 tmpreg = PWR->CR;
\ 00000002 .... LDR.N R2,??DataTable7_2 ;; 0x40007000
\ 00000004 1268 LDR R2,[R2, #+0]
\ 00000006 1100 MOVS R1,R2
163 /* Clear PLS[7:5] bits */
164 tmpreg &= CR_PLS_MASK;
\ 00000008 31F0E001 BICS R1,R1,#0xE0
165 /* Set PLS[7:5] bits according to PWR_PVDLevel value */
166 tmpreg |= PWR_PVDLevel;
\ 0000000C 0143 ORRS R1,R0,R1
167 /* Store the new value */
168 PWR->CR = tmpreg;
\ 0000000E .... LDR.N R2,??DataTable7_2 ;; 0x40007000
\ 00000010 1160 STR R1,[R2, #+0]
169 }
\ 00000012 7047 BX LR ;; return
170
171 /**
172 * @brief Enables or disables the WakeUp Pin functionality.
173 * @param NewState: new state of the WakeUp Pin functionality.
174 * This parameter can be: ENABLE or DISABLE.
175 * @retval None
176 */
\ In section .text, align 2, keep-with-next
177 void PWR_WakeUpPinCmd(FunctionalState NewState)
178 {
179 /* Check the parameters */
180 assert_param(IS_FUNCTIONAL_STATE(NewState));
181 *(__IO uint32_t *) CSR_EWUP_BB = (uint32_t)NewState;
\ PWR_WakeUpPinCmd:
\ 00000000 .... LDR.N R1,??DataTable7_3 ;; 0x420e00a0
\ 00000002 C0B2 UXTB R0,R0 ;; ZeroExt R0,R0,#+24,#+24
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