📄 stm32f10x_cec.lst
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###############################################################################
# #
# IAR ANSI C/C++ Compiler V6.10.2.52244/W32 for ARM 07/Aug/2011 12:10:33 #
# Copyright 1999-2010 IAR Systems AB. #
# #
# Cpu mode = thumb #
# Endian = little #
# Source file = F:\stm32\我的程序\Micrium\Software\EWARM\BSP\ST\STM32F10 #
# x_StdPeriph_Driver\src\stm32f10x_cec.c #
# Command line = F:\stm32\我的程序\Micrium\Software\EWARM\BSP\ST\STM32F10 #
# x_StdPeriph_Driver\src\stm32f10x_cec.c -D #
# USE_STDPERIPH_DRIVER -D STM32F10X_CL -lCN #
# F:\stm32\我的程序\Micrium\Software\EWARM\OS-II\Flash\Lis #
# t\ -o F:\stm32\我的程序\Micrium\Software\EWARM\OS-II\Fla #
# sh\Obj\ --no_cse --no_unroll --no_inline #
# --no_code_motion --no_tbaa --no_clustering #
# --no_scheduling --debug --endian=little --cpu=Cortex-M3 #
# -e --fpu=None --dlib_config #
# D:\arm\INC\c\DLib_Config_Normal.h -I #
# F:\stm32\我的程序\Micrium\Software\EWARM\OS-II\APP\ -I #
# F:\stm32\我的程序\Micrium\Software\EWARM\OS-II\..\BSP\ #
# -I F:\stm32\我的程序\Micrium\Software\EWARM\OS-II\..\BSP #
# \ST\CMSIS\CM3\CoreSupport\ -I #
# F:\stm32\我的程序\Micrium\Software\EWARM\OS-II\..\BSP\ST #
# \CMSIS\CM3\DeviceSupport\ST\STM32F10x\ -I #
# F:\stm32\我的程序\Micrium\Software\EWARM\OS-II\..\BSP\ST #
# \STM32F10x_StdPeriph_Driver\inc\ -I #
# F:\stm32\我的程序\Micrium\Software\EWARM\OS-II\..\BSP\uC #
# OS-II\ -I F:\stm32\我的程序\Micrium\Software\EWARM\OS-II #
# \..\..\uCOS-II\Ports\ARM-Cortex-M3\Generic\IAR\ -I #
# F:\stm32\我的程序\Micrium\Software\EWARM\OS-II\..\..\uCO #
# S-II\Source\ -I F:\stm32\我的程序\Micrium\Software\EWARM #
# \OS-II\..\..\uC-LIB\ -I F:\stm32\我的程序\Micrium\Softwa #
# re\EWARM\OS-II\..\..\uC-LIB\Ports\ARM-Cortex-M3\IAR\ -I #
# F:\stm32\我的程序\Micrium\Software\EWARM\OS-II\..\..\uC- #
# CPU\ -I F:\stm32\我的程序\Micrium\Software\EWARM\OS-II\. #
# .\..\uC-CPU\ARM-Cortex-M3\IAR\ -On --use_c++_inline #
# List file = F:\stm32\我的程序\Micrium\Software\EWARM\OS-II\Flash\Lis #
# t\stm32f10x_cec.lst #
# Object file = F:\stm32\我的程序\Micrium\Software\EWARM\OS-II\Flash\Obj #
# \stm32f10x_cec.o #
# #
# #
###############################################################################
F:\stm32\我的程序\Micrium\Software\EWARM\BSP\ST\STM32F10x_StdPeriph_Driver\src\stm32f10x_cec.c
1 /**
2 ******************************************************************************
3 * @file stm32f10x_cec.c
4 * @author MCD Application Team
5 * @version V3.4.0
6 * @date 10/15/2010
7 * @brief This file provides all the CEC firmware functions.
8 ******************************************************************************
9 * @copy
10 *
11 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
12 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
13 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
14 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
15 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
16 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
17 *
18 * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
19 */
20
21 /* Includes ------------------------------------------------------------------*/
22 #include "stm32f10x_cec.h"
23 #include "stm32f10x_rcc.h"
24
25 /** @addtogroup STM32F10x_StdPeriph_Driver
26 * @{
27 */
28
29 /** @defgroup CEC
30 * @brief CEC driver modules
31 * @{
32 */
33
34 /** @defgroup CEC_Private_TypesDefinitions
35 * @{
36 */
37
38 /**
39 * @}
40 */
41
42
43 /** @defgroup CEC_Private_Defines
44 * @{
45 */
46
47 /* ------------ CEC registers bit address in the alias region ----------- */
48 #define CEC_OFFSET (CEC_BASE - PERIPH_BASE)
49
50 /* --- CFGR Register ---*/
51
52 /* Alias word address of PE bit */
53 #define CFGR_OFFSET (CEC_OFFSET + 0x00)
54 #define PE_BitNumber 0x00
55 #define CFGR_PE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (PE_BitNumber * 4))
56
57 /* Alias word address of IE bit */
58 #define IE_BitNumber 0x01
59 #define CFGR_IE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (IE_BitNumber * 4))
60
61 /* --- CSR Register ---*/
62
63 /* Alias word address of TSOM bit */
64 #define CSR_OFFSET (CEC_OFFSET + 0x10)
65 #define TSOM_BitNumber 0x00
66 #define CSR_TSOM_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TSOM_BitNumber * 4))
67
68 /* Alias word address of TEOM bit */
69 #define TEOM_BitNumber 0x01
70 #define CSR_TEOM_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEOM_BitNumber * 4))
71
72 #define CFGR_CLEAR_Mask (uint8_t)(0xF3) /* CFGR register Mask */
73 #define FLAG_Mask ((uint32_t)0x00FFFFFF) /* CEC FLAG mask */
74
75 /**
76 * @}
77 */
78
79
80 /** @defgroup CEC_Private_Macros
81 * @{
82 */
83
84 /**
85 * @}
86 */
87
88
89 /** @defgroup CEC_Private_Variables
90 * @{
91 */
92
93 /**
94 * @}
95 */
96
97
98 /** @defgroup CEC_Private_FunctionPrototypes
99 * @{
100 */
101
102 /**
103 * @}
104 */
105
106
107 /** @defgroup CEC_Private_Functions
108 * @{
109 */
110
111 /**
112 * @brief Deinitializes the CEC peripheral registers to their default reset
113 * values.
114 * @param None
115 * @retval None
116 */
\ In section .text, align 2, keep-with-next
117 void CEC_DeInit(void)
118 {
\ CEC_DeInit:
\ 00000000 80B5 PUSH {R7,LR}
119 /* Enable CEC reset state */
120 RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, ENABLE);
\ 00000002 0121 MOVS R1,#+1
\ 00000004 5FF08040 MOVS R0,#+1073741824
\ 00000008 ........ BL RCC_APB1PeriphResetCmd
121 /* Release CEC from reset state */
122 RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, DISABLE);
\ 0000000C 0021 MOVS R1,#+0
\ 0000000E 5FF08040 MOVS R0,#+1073741824
\ 00000012 ........ BL RCC_APB1PeriphResetCmd
123 }
\ 00000016 01BD POP {R0,PC} ;; return
124
125
126 /**
127 * @brief Initializes the CEC peripheral according to the specified
128 * parameters in the CEC_InitStruct.
129 * @param CEC_InitStruct: pointer to an CEC_InitTypeDef structure that
130 * contains the configuration information for the specified
131 * CEC peripheral.
132 * @retval None
133 */
\ In section .text, align 2, keep-with-next
134 void CEC_Init(CEC_InitTypeDef* CEC_InitStruct)
135 {
136 uint16_t tmpreg = 0;
\ CEC_Init:
\ 00000000 0021 MOVS R1,#+0
137
138 /* Check the parameters */
139 assert_param(IS_CEC_BIT_TIMING_ERROR_MODE(CEC_InitStruct->CEC_BitTimingMode));
140 assert_param(IS_CEC_BIT_PERIOD_ERROR_MODE(CEC_InitStruct->CEC_BitPeriodMode));
141
142 /*---------------------------- CEC CFGR Configuration -----------------*/
143 /* Get the CEC CFGR value */
144 tmpreg = CEC->CFGR;
\ 00000002 .... LDR.N R2,??DataTable12 ;; 0x40007800
\ 00000004 1268 LDR R2,[R2, #+0]
\ 00000006 1100 MOVS R1,R2
145
146 /* Clear BTEM and BPEM bits */
147 tmpreg &= CFGR_CLEAR_Mask;
\ 00000008 11F0F301 ANDS R1,R1,#0xF3
148
149 /* Configure CEC: Bit Timing Error and Bit Period Error */
150 tmpreg |= (uint16_t)(CEC_InitStruct->CEC_BitTimingMode | CEC_InitStruct->CEC_BitPeriodMode);
\ 0000000C 0288 LDRH R2,[R0, #+0]
\ 0000000E 4388 LDRH R3,[R0, #+2]
\ 00000010 1A43 ORRS R2,R3,R2
\ 00000012 1143 ORRS R1,R2,R1
151
152 /* Write to CEC CFGR register*/
153 CEC->CFGR = tmpreg;
\ 00000014 .... LDR.N R2,??DataTable12 ;; 0x40007800
\ 00000016 89B2 UXTH R1,R1 ;; ZeroExt R1,R1,#+16,#+16
\ 00000018 1160 STR R1,[R2, #+0]
154
155 }
\ 0000001A 7047 BX LR ;; return
156
157 /**
158 * @brief Enables or disables the specified CEC peripheral.
159 * @param NewState: new state of the CEC peripheral.
160 * This parameter can be: ENABLE or DISABLE.
161 * @retval None
162 */
\ In section .text, align 2, keep-with-next
163 void CEC_Cmd(FunctionalState NewState)
164 {
165 /* Check the parameters */
166 assert_param(IS_FUNCTIONAL_STATE(NewState));
167
168 *(__IO uint32_t *) CFGR_PE_BB = (uint32_t)NewState;
\ CEC_Cmd:
\ 00000000 .... LDR.N R1,??DataTable12_1 ;; 0x420f0000
\ 00000002 C0B2 UXTB R0,R0 ;; ZeroExt R0,R0,#+24,#+24
\ 00000004 0860 STR R0,[R1, #+0]
169
170 if(NewState == DISABLE)
\ 00000006 C0B2 UXTB R0,R0 ;; ZeroExt R0,R0,#+24,#+24
\ 00000008 0028 CMP R0,#+0
\ 0000000A 03D1 BNE.N ??CEC_Cmd_0
171 {
172 /* Wait until the PE bit is cleared by hardware (Idle Line detected) */
173 while((CEC->CFGR & CEC_CFGR_PE) != (uint32_t)RESET)
\ ??CEC_Cmd_1:
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