📄 stm32f10x_can.lst
字号:
161
162 /* exit from sleep mode */
163 CANx->MCR &= (~(uint32_t)CAN_MCR_SLEEP);
\ 00000008 1468 LDR R4,[R2, #+0]
\ 0000000A 34F00204 BICS R4,R4,#0x2
\ 0000000E 1460 STR R4,[R2, #+0]
164
165 /* Request initialisation */
166 CANx->MCR |= CAN_MCR_INRQ ;
\ 00000010 1468 LDR R4,[R2, #+0]
\ 00000012 54F00104 ORRS R4,R4,#0x1
\ 00000016 1460 STR R4,[R2, #+0]
167
168 /* Wait the acknowledge */
169 while (((CANx->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) && (wait_ack != INAK_TIMEOUT))
\ ??CAN_Init_0:
\ 00000018 5468 LDR R4,[R2, #+4]
\ 0000001A E407 LSLS R4,R4,#+31
\ 0000001C 05D4 BMI.N ??CAN_Init_1
\ 0000001E 4FF6FF74 MOVW R4,#+65535
\ 00000022 A342 CMP R3,R4
\ 00000024 01D0 BEQ.N ??CAN_Init_1
170 {
171 wait_ack++;
\ 00000026 5B1C ADDS R3,R3,#+1
\ 00000028 F6E7 B.N ??CAN_Init_0
172 }
173
174 /* ...and check acknowledged */
175 if ((CANx->MSR & CAN_MSR_INAK) != CAN_MSR_INAK)
\ ??CAN_Init_1:
\ 0000002A 5468 LDR R4,[R2, #+4]
\ 0000002C E407 LSLS R4,R4,#+31
\ 0000002E 02D4 BMI.N ??CAN_Init_2
176 {
177 InitStatus = CANINITFAILED;
\ 00000030 0024 MOVS R4,#+0
\ 00000032 2000 MOVS R0,R4
\ 00000034 6DE0 B.N ??CAN_Init_3
178 }
179 else
180 {
181 /* Set the time triggered communication mode */
182 if (CAN_InitStruct->CAN_TTCM == ENABLE)
\ ??CAN_Init_2:
\ 00000036 8C79 LDRB R4,[R1, #+6]
\ 00000038 012C CMP R4,#+1
\ 0000003A 04D1 BNE.N ??CAN_Init_4
183 {
184 CANx->MCR |= CAN_MCR_TTCM;
\ 0000003C 1468 LDR R4,[R2, #+0]
\ 0000003E 54F08004 ORRS R4,R4,#0x80
\ 00000042 1460 STR R4,[R2, #+0]
\ 00000044 03E0 B.N ??CAN_Init_5
185 }
186 else
187 {
188 CANx->MCR &= ~(uint32_t)CAN_MCR_TTCM;
\ ??CAN_Init_4:
\ 00000046 1468 LDR R4,[R2, #+0]
\ 00000048 34F08004 BICS R4,R4,#0x80
\ 0000004C 1460 STR R4,[R2, #+0]
189 }
190
191 /* Set the automatic bus-off management */
192 if (CAN_InitStruct->CAN_ABOM == ENABLE)
\ ??CAN_Init_5:
\ 0000004E CC79 LDRB R4,[R1, #+7]
\ 00000050 012C CMP R4,#+1
\ 00000052 04D1 BNE.N ??CAN_Init_6
193 {
194 CANx->MCR |= CAN_MCR_ABOM;
\ 00000054 1468 LDR R4,[R2, #+0]
\ 00000056 54F04004 ORRS R4,R4,#0x40
\ 0000005A 1460 STR R4,[R2, #+0]
\ 0000005C 03E0 B.N ??CAN_Init_7
195 }
196 else
197 {
198 CANx->MCR &= ~(uint32_t)CAN_MCR_ABOM;
\ ??CAN_Init_6:
\ 0000005E 1468 LDR R4,[R2, #+0]
\ 00000060 34F04004 BICS R4,R4,#0x40
\ 00000064 1460 STR R4,[R2, #+0]
199 }
200
201 /* Set the automatic wake-up mode */
202 if (CAN_InitStruct->CAN_AWUM == ENABLE)
\ ??CAN_Init_7:
\ 00000066 0C7A LDRB R4,[R1, #+8]
\ 00000068 012C CMP R4,#+1
\ 0000006A 04D1 BNE.N ??CAN_Init_8
203 {
204 CANx->MCR |= CAN_MCR_AWUM;
\ 0000006C 1468 LDR R4,[R2, #+0]
\ 0000006E 54F02004 ORRS R4,R4,#0x20
\ 00000072 1460 STR R4,[R2, #+0]
\ 00000074 03E0 B.N ??CAN_Init_9
205 }
206 else
207 {
208 CANx->MCR &= ~(uint32_t)CAN_MCR_AWUM;
\ ??CAN_Init_8:
\ 00000076 1468 LDR R4,[R2, #+0]
\ 00000078 34F02004 BICS R4,R4,#0x20
\ 0000007C 1460 STR R4,[R2, #+0]
209 }
210
211 /* Set the no automatic retransmission */
212 if (CAN_InitStruct->CAN_NART == ENABLE)
\ ??CAN_Init_9:
\ 0000007E 4C7A LDRB R4,[R1, #+9]
\ 00000080 012C CMP R4,#+1
\ 00000082 04D1 BNE.N ??CAN_Init_10
213 {
214 CANx->MCR |= CAN_MCR_NART;
\ 00000084 1468 LDR R4,[R2, #+0]
\ 00000086 54F01004 ORRS R4,R4,#0x10
\ 0000008A 1460 STR R4,[R2, #+0]
\ 0000008C 03E0 B.N ??CAN_Init_11
215 }
216 else
217 {
218 CANx->MCR &= ~(uint32_t)CAN_MCR_NART;
\ ??CAN_Init_10:
\ 0000008E 1468 LDR R4,[R2, #+0]
\ 00000090 34F01004 BICS R4,R4,#0x10
\ 00000094 1460 STR R4,[R2, #+0]
219 }
220
221 /* Set the receive FIFO locked mode */
222 if (CAN_InitStruct->CAN_RFLM == ENABLE)
\ ??CAN_Init_11:
\ 00000096 8C7A LDRB R4,[R1, #+10]
\ 00000098 012C CMP R4,#+1
\ 0000009A 04D1 BNE.N ??CAN_Init_12
223 {
224 CANx->MCR |= CAN_MCR_RFLM;
\ 0000009C 1468 LDR R4,[R2, #+0]
\ 0000009E 54F00804 ORRS R4,R4,#0x8
\ 000000A2 1460 STR R4,[R2, #+0]
\ 000000A4 03E0 B.N ??CAN_Init_13
225 }
226 else
227 {
228 CANx->MCR &= ~(uint32_t)CAN_MCR_RFLM;
\ ??CAN_Init_12:
\ 000000A6 1468 LDR R4,[R2, #+0]
\ 000000A8 34F00804 BICS R4,R4,#0x8
\ 000000AC 1460 STR R4,[R2, #+0]
229 }
230
231 /* Set the transmit FIFO priority */
232 if (CAN_InitStruct->CAN_TXFP == ENABLE)
\ ??CAN_Init_13:
\ 000000AE CC7A LDRB R4,[R1, #+11]
\ 000000B0 012C CMP R4,#+1
\ 000000B2 04D1 BNE.N ??CAN_Init_14
233 {
234 CANx->MCR |= CAN_MCR_TXFP;
\ 000000B4 1468 LDR R4,[R2, #+0]
\ 000000B6 54F00404 ORRS R4,R4,#0x4
\ 000000BA 1460 STR R4,[R2, #+0]
\ 000000BC 03E0 B.N ??CAN_Init_15
235 }
236 else
237 {
238 CANx->MCR &= ~(uint32_t)CAN_MCR_TXFP;
\ ??CAN_Init_14:
\ 000000BE 1468 LDR R4,[R2, #+0]
\ 000000C0 34F00404 BICS R4,R4,#0x4
\ 000000C4 1460 STR R4,[R2, #+0]
239 }
240
241 /* Set the bit timing register */
242 CANx->BTR = (uint32_t)((uint32_t)CAN_InitStruct->CAN_Mode << 30) | ((uint32_t)CAN_InitStruct->CAN_SJW << 24) |
243 ((uint32_t)CAN_InitStruct->CAN_BS1 << 16) | ((uint32_t)CAN_InitStruct->CAN_BS2 << 20) |
244 ((uint32_t)CAN_InitStruct->CAN_Prescaler - 1);
\ ??CAN_Init_15:
\ 000000C6 8C78 LDRB R4,[R1, #+2]
\ 000000C8 CD78 LDRB R5,[R1, #+3]
\ 000000CA 2D06 LSLS R5,R5,#+24
\ 000000CC 55EA8474 ORRS R4,R5,R4, LSL #+30
\ 000000D0 0D79 LDRB R5,[R1, #+4]
\ 000000D2 54EA0544 ORRS R4,R4,R5, LSL #+16
\ 000000D6 4D79 LDRB R5,[R1, #+5]
\ 000000D8 54EA0554 ORRS R4,R4,R5, LSL #+20
\ 000000DC 0D88 LDRH R5,[R1, #+0]
\ 000000DE 6D1E SUBS R5,R5,#+1
\ 000000E0 2C43 ORRS R4,R5,R4
\ 000000E2 D461 STR R4,[R2, #+28]
245
246 /* Request leave initialisation */
247 CANx->MCR &= ~(uint32_t)CAN_MCR_INRQ;
\ 000000E4 1468 LDR R4,[R2, #+0]
\ 000000E6 6408 LSRS R4,R4,#+1
\ 000000E8 6400 LSLS R4,R4,#+1
\ 000000EA 1460 STR R4,[R2, #+0]
248
249 /* Wait the acknowledge */
250 wait_ack = 0x00;
\ 000000EC 0024 MOVS R4,#+0
\ 000000EE 2300 MOVS R3,R4
251
252 while (((CANx->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) && (wait_ack != INAK_TIMEOUT))
\ ??CAN_Init_16:
\ 000000F0 5468 LDR R4,[R2, #+4]
\ 000000F2 E407 LSLS R4,R4,#+31
\ 000000F4 05D5 BPL.N ??CAN_Init_17
\ 000000F6 4FF6FF74 MOVW R4,#+65535
\ 000000FA A342 CMP R3,R4
\ 000000FC 01D0 BEQ.N ??CAN_Init_17
253 {
254 wait_ack++;
\ 000000FE 5B1C ADDS R3,R3,#+1
\ 00000100 F6E7 B.N ??CAN_Init_16
255 }
256
257 /* ...and check acknowledged */
258 if ((CANx->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)
\ ??CAN_Init_17:
\ 00000102 5468 LDR R4,[R2, #+4]
\ 00000104 E407 LSLS R4,R4,#+31
\ 00000106 02D5 BPL.N ??CAN_Init_18
259 {
260 InitStatus = CANINITFAILED;
\ 00000108 0024 MOVS R4,#+0
\ 0000010A 2000 MOVS R0,R4
\ 0000010C 01E0 B.N ??CAN_Init_3
261 }
262 else
263 {
264 InitStatus = CANINITOK ;
\ ??CAN_Init_18:
\ 0000010E 0124 MOVS R4,#+1
\ 00000110 2000 MOVS R0,R4
265 }
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